Offset Reduction Techniques in High-speed Analog–to-digital Converters

by Figueiredo, Pedro M.; Vital, Joao C.

• ISBN13: 9781402097157
• ISBN10: 1402097158
• Format: Hardcover
• Copyright: 2009-05-01
• Publisher: Springer Verlag

Summary

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.

Author Biography

Pedro Figueiredo received the degrees of Licenciado and Doutor (PhD) in Electrical and Computer Engineering in 1999 and 2006, respectively, from the Instituto Superior T+¬cnico (IST), Lisbon, Portugal. From 1997 to 1999, he was with the Analog and Mixed-Mode Circuits Group in the Institute for Systems and Computer Engineering (INESC), Lisbon, Portugal, where he worked on low-noise logic families and high-speed Analog-to-Digital Converters.In 1999, he joined Chipidea - Microelectr+¦nica, where he currently leads the group responsible for the design of Analog-to-Digital Converters. His main research interests are in the area of analog and mixed-signal circuits, with emphasis on high-speed data conversion and design automation. He has 10 publications in international journals and conferences.Jo+úo Vital received the degrees of Licenciado, Mestre and Doutor (PhD) in Electrical and Computer Engineering in 1986, 1990 and 1994, respectively, all from the Instituto Superior T+¬cnico (IST), Lisboa, Portugal. He is a Co-founder of Chipidea - Microelectronica in 1997, and currently serves as Vice-President of Data Conversion, leading the Data Conversion Solutions Division of Chipidea to provide competitive solutions towards the demanding markets of Broadband Wireless Communications and Video. His main scientific interests are in the area of analog and mixed-signal integrated-circuit design, with a focus on data conversion. He developed research work in the University of Pavia, Italy, in the University of California - Los Angeles, USA, and in the Oregon State University, USA, also in 1990. He has over 50 publications in international journals, book chapters and conferences and is a co-holder of an European and US Patent filed by British Telecom.

Table of Contents

Preface

List of Symbols and Abbreviations

High-Speed ADC Architectures

Introduction

The Analog-to-Digital Converter

Flash ADCs

Two-Step Flash ADCs

Folding and Interpolation ADCs

Building Blocks of CMOS High-Speed ADCs

Averaging Technique - DC Analysis and Termination

Introduction

Published Studies on the Averaging Technique

Output Voltage and Gain

Effect of Mismatches - INL and DNL

Averaging in Folding Circuits

Considerations About the Yield

Termination of the Averaging Network

Averaging Technique - Transient Analysis and Automated Design

Introduction

Flash ADC Architecture

Output Voltage and Gain

Effect of Mismatches

Design of Averaged Pre-Amplifier Stages in Flash ADCs

Integrated Prototypes using Averaging

Introduction

7-bit 120 MS/s I/Q flash ADC

10-bit 100 MS/s Folding and Interpolation ADC

Offset Cancellation Methods

Introduction

Offset Cancellation Techniques

New Offset Cancellation Technique

6-bit 1 GHz Two-Step Subranging ADC

Conclusions

Overview of the Research Work

Averaging with Piecewise Linear Differential Pairs

Introduction

Output Voltage and Gain

Effect of Mismatches - INL and DNL

Mismatches in the Resistors of the Aveaging Network

Introduction

Mismatches in Resistors R.0

Mismatches in Resistors R1

Averaging in Folding Stages

Introduction

Equivalence Between Circular and Infinite Networks

Output Voltage and Gain

Effect of Mismatches

References

Index

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