PCI Express* Electrical Interconnect Design

by Coleman, David; Gardiner, Scott; Kolbehdari, Mohammad; Peters, Stephen

• ISBN13: 9780974364995
• ISBN10: 0974364991
• Edition: Illus.
• Format: Paperback
• Copyright: 2004-10-01
• Publisher: Intel Pr

Table of Contents

iii Contents Acknowledgments ix Chapter 1 PCI Express_ Electrical Architecture 1 Electrical Advantages and Built-in Capabilities 3 Signal Performance 3 Clocking 7 Electromagnetic Compatibility 8 AC Coupling 11 Ports, Links, and Lanes 11 Link Training 12 Detect 12 Data Rate Negotiation 13 Polarity Inversion 14 Lane-to-Lane De-skew 14 Lane Number and Width Negotiation 16 Lane Reversal 17 PCI Express_ Electrical Specifications 18 Topology and Interconnect Overview 18 A Paradigm Shift 20 Signal Integrity Essentials 21 iv PCI Express_ Electrical Interconnect Design Chapter 2 Signal Integrity Design Modeling 33 Component Loss-based Method 33 PCI Express_ Interconnect Simulation Models 34 Package and Circuit Characterization 35 FCBGA and WB-BGA Package Types 35 Package and Die Validation Model 39 Driver Model 40 IBIS Model 41 On-die Decoupling Capacitance 42 Receiver Model 42 PCB Modeling 42 PCB Interconnect Model 43 W-element and N-element Models 45 Signal Integrity Phenomena 49 Loss 50 Crosstalk 52 Reflections 54 AC Coupling Capacitance 55 PCB Vias Model 55 Connectors 57 Die-to-Die Simulation Model 57 Time Domain Simulation Model 57 Frequency Domain Simulation Model 58 Power Delivery Network 59 Power Delivery Analysis 59 PDN Drivers 60 PDN Time Domain Design Parameters 60 PDN Frequency Domain Design Parameters 60 PDN Modeling 61 Driver and On-die Capacitance 62 Package and PCB Models 62 Decoupling Capacitor Model 62 Vias and Socket Model 62 Power Supply Model 63 PDN Simulation Method 63 Simplified PDN Model 64 Contents v Chapter 3 Time Domain Analysis 65 Voltage Modes 66 Mode Conversion 66 Transmitter Parameters 67 Receiver Parameters 69 Excitation Pattern 71 ISI Pattern 72 Crosstalk Pattern 72 SSO Pattern 74 Data Bit-Stream Length 74 DOE Analysis 74 DOE Input Parameters 75 Order of Curve Fitting 76 Drive Inputs 76 Interconnect Inputs 77 Receiver Parameters 77 DOE Example 77 Margin Mode Computation 82 Eye Measuring 82 System Model and Add-in Card Topologies 85 Eye Diagram and Compliance Jitter 86 Driver and Receiver Eye Requirements 86 Driver and Receiver Simulation Topology 88 Chapter 4 Frequency Domain Analysis 89 Single-ended and Differential S-parameters 90 Frequency Domain Interconnect Model 93 Parameters of Measurement and Simulation 93 Multi-pair Aggressor-Victim Model 93 Excitation Matrix 95 Differential Mode Voltage 96 Common Mode Voltages 97 Impedance Mismatch 98 Multi-segment Topology and the ABCD Method 99 Chain or ABCD Matrix Method 99 S-parameters Versus ABCD Matrix 100 S-parameters of the Cascaded Multi-segment 101 S-parameters with Load and Source 102 vi PCI Express_ Electrical Interconnect Design Mason_s Rule 103 Loss Budget Partitioning 104 Correlation Between Frequency and Time Domains 105 Differential Insertion Loss 105 Common Mode Losses 106 Chapter 5 Successful System Layout Design_ Getting Started 107 System Topology Overviews 108 Taking Advantage of the PCI Express_ Specification 112 Connectivity Rules 112 Bowtie Topology Considerations 114 System-level Floor-planning 117 Routing Length Recommendations and Restrictions 118 System Reference Clock Considerations 120 AC Coupling Capacitors 124 Cable Considerations for System Design 128 ExpressCard_ Internal Cable Interface 129 Riser and Daughter Card Implementations 132 PCI Express_ Extension Risers 132 Daughter Cards for ExpressCard_ Modules 134 Other System Design Considerations: Power Delivery, Thermal and Acoustical Management, and EMI 136 Power Delivery 136 Thermal and Acoustical Manag