Pci System Architecture

by MindShare, Inc.; Shanley, Tom; Anderson, Don

• ISBN13: 9780201309744
• ISBN10: 0201309742
• Edition: 4th
• Format: Paperback
• Copyright: 1999-06-10
• Publisher: Addison-Wesley Professional

Summary

PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor. This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification. This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers. In addition, you will find specific information on such key topics as: bull; bull;Hot-Plug Specification bull;Power management bull;CompactPCI bull;The 64-bit PCI Extension bull;66 MHz PCI Implementation bull;Expansion ROMs bull;PCI-to-PCI Bridge and the PCI BIOS bull;Add-in cards and connectors bull;Bus arbitration bull;Reflected-wave switching bull;Early transactionend bull;Fast back-to-back and stepping Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions. Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology. The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmers perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

Author Biography

Tom Shanley is one of the world's foremost authorities on PC system architecture and has personally trained thousands of engineers in hardware and software design. Don Anderson passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.

Table of Contents

About This Book
The MindShare Architecture Series	1	(1)
Organization of This Book	2	(1)
Designation of Specification Changes	3	(1)
Cautionary Note	3	(1)
Who this Book is For	4	(1)
Prerequisite Knowledge	4	(1)
Object Size Designations	4	(1)
Documentation Conventions	5	(1)
Hex Notation	5	(1)
Binary Notation	5	(1)
Decimal Notation	5	(1)
Signal Name Representation	5	(1)
Identification of Bit Fields (logical groups of bits or signals)	6	(1)
We Want Your Feedback	6	(1)
Intro To PCI
PCI Bus History	7	(1)
PCI Bus Features	8	(4)
PCI Device vs. Function	12	(1)
Specifications Book is Based On	13	(1)
Obtaining PCI Bus Specification(s)	13	(2)
Intro to PCI Bus Operation
Burst Transfer	15	(2)
Initiator, Target and Agents	17	(1)
Single- Vs. Multi-Function PCI Devices	17	(1)
PCI Bus Clock	17	(1)
Address Phase	18	(1)
Claiming the Transaction	19	(1)
Data Phase(s)	19	(1)
Transaction Duration	20	(1)
Transaction Completion and Return of Bus to Idle State	20	(1)
Response to Illegal Behavior	20	(1)
``Green'' Machine	21	(2)
Intro to Reflected-Wave Switching
Each Trace Is a Transmission Line	23	(1)
Old Method: Incident-Wave Switching	24	(2)
PCI Method: Reflected-Wave Switching	26	(2)
CLK Signal	28	(1)
RST#/REQ64# Timing	29	(1)
Slower Clock Permits Longer Bus	30	(1)
The Signal Groups
Introduction	31	(3)
System Signals	34	(3)
PCI Clock Signal (CLK)	34	(1)
CLKRUN# Signal	35	(1)
Description	35	(1)
Achieving CLKRUN# Benefit On Add-In Cards	36	(1)
Reset Signal (RST#)	37	(1)
Address/Data Bus, Command Bus, and Byte Enables	37	(3)
Preventing Excessive Current Drain	40	(1)
Transaction Control Signals	41	(2)
Arbitration Signals	43	(1)
Interrupt Request Signals	43	(1)
Error Reporting Signals	43	(3)
Data Parity Error	44	(1)
System Error	45	(1)
Cache Support (Snoop Result) Signals	46	(1)
64-bit Extension Signals	47	(1)
Resource Locking	48	(1)
JTAG/Boundary Scan Signals	48	(1)
Interrupt Request Pins	49	(1)
PME# and 3.3 Vaux	49	(1)
Sideband Signals	49	(1)
Signal Types	50	(2)
Device Cannot Simultaneously Drive and Receive a Signal	52	(1)
Central Resource Functions	52	(1)
Subtractive Decode (by ISA Bridge)	53	(4)
Background	53	(3)
Tuning Subtractive Decoder	56	(1)
Reading Timing Diagrams	57	(2)
PCI Bus Arbitration
Arbiter	59	(1)
Arbitration Algorithm	60	(3)
Example Arbiter with Fairness	63	(2)
Master Wishes To Perform More Than One Transaction	65	(1)
Hidden Bus Arbitration	65	(1)
Bus Parking	65	(2)
Request/Grant Timing	67	(1)
Example of Arbitration Between Two Masters	68	(3)
State of REQ# and GNT# During RST#	71	(1)
Pullups On REQ# From Add-In Connectors	71	(1)
Broken Master	72	(1)
Master and Target Latency
Mandatory Delay Before First Transaction Initiated	73	(1)
Bus Access Latency	74	(2)
Pre-2.1 Devices Can Be Bad Boys	76	(1)
Preventing Master from Monopolizing the Bus	76	(5)
Master Must Transfer Data Within 8 CLKs	76	(1)
IRDY# Deasserted In Clock After Last Data Transfer	77	(1)
Latency Timer Keeps Master From Monopolizing Bus	78	(1)
Location and Purpose of Master Latency Timer	78	(1)
How LT Works	79	(1)
Is Implementation of LT Register Mandatory?	80	(1)
Can LT Value Be Hardwired?	80	(1)
How Does Software Determine Timeslice To Be Allocated To Master?	80	(1)
Treatment of Memory Write and Invalidate Command	80	(1)
Preventing Target From Monopolizing Bus	81	(13)
General	81	(1)
Target Must Transfer Data Expeditiously	81	(1)
General	81	(1)
The First Data Phase Rule	82	(1)
General	82	(1)
Master's Response To Retry	82	(1)
Sometimes Target Can't Transfer First Data Within 16 CLKs	82	(1)
Target Frequently Can't Transfer First Data Within 16 CLKs	83	(1)
Two Exceptions To First Data Phase Rule	83	(1)
Subsequent Data Phase Rule	84	(1)
General	84	(1)
In Data Phase and Cannot Transfer Data Within 8 Clocks	84	(1)
OK In This Data Phase, But Can't Meet Rule In Next One	84	(1)
Master's Response To a Disconnect	84	(1)
Target's Subsequent Latency and Master's Latency Timer	85	(1)
Target Latency During Initialization Time	85	(1)
Initialization Time vs. Run Time	85	(1)
Definition of Initialization Time and Behavior (Before 2.2)	85	(1)
Definition of Initialization Time and Behavior (2.2)	86	(1)
Delayed Transactions	86	(1)
The Problem	86	(1)
The Solution	86	(2)
Information Memorized	88	(1)
Master and Target Actions During Delayed Transaction	88	(1)
Commands That Can Use Delayed Transactions	89	(1)
Request Not Completed and Targeted Again	89	(1)
Special Cycle Monitoring While Processing Request	89	(1)
Discard of Delayed Requests	90	(1)
Multiple Delayed Request from Same Master	90	(1)
Request Queuing In Target	90	(1)
Discard of Delayed Completions	91	(1)
Read From Prefetchable Memory	91	(1)
Master Tardy In Repeating Transaction	91	(1)
Reporting Discard of Data On a Read	91	(1)
Handling Multiple Data Phases	92	(1)
Master or Target Abort Handling	92	(1)
What Is Prefetchable Memory?	93	(1)
Delayed Read Prefetch	93	(1)
Posting Improves Memory Write Performance	94	(2)
General	94	(1)
Combining	94	(1)
Byte Merging	95	(1)
Collapsing Is Forbidden	95	(1)
Memory Write Maximum Completion Limit	96	(1)
Transaction Ordering and Deadlocks	97	(2)
The Commands
Introduction	99	(1)
Interrupt Acknowledge Command	100	(7)
Introduction	100	(1)
Background	101	(3)
Host/PCI Bridge Handling of Interrupt Acknowledge	104	(1)
PCI Interrupt Acknowledge Transaction	104	(2)
PowerPC PReP Handling of INTR	106	(1)
Special Cycle Command	107	(5)
General	107	(2)
Special Cycle Generation Under Software Control	109	(1)
Special Cycle Transaction	110	(1)
Single-Data Phase Special Cycle Transaction	110	(2)
Multiple Data Phase Special Cycle Transaction	112	(1)
IO Read and Write Commands	112	(1)
Accessing Memory	113	(8)
Target Support For Bulk Commands Is Optional	113	(1)
Cache Line Size Register And the Bulk Commands	113	(2)
Bulk Commands Are Optional Performance Enhancement Tools	115	(1)
Bridges Must Discard Prefetched Data Not Consumed By Master	116	(1)
Writing Memory	117	(1)
Memory Write Command	117	(1)
Memory Write-and-Invalidate Command	117	(1)
Problem	117	(1)
Description of Memory Write-and-Invalidate Command	118	(1)
More Information On Memory Transfers	119	(2)
Configuration Read and Write Commands	121	(1)
Dual-Address Cycle	121	(1)
Reserved Bus Commands	121	(2)
Read Transfers
Some Basic Rules For Both Reads and Writes	123	(1)
Parity	124	(1)
Example Single Data Phase Read	124	(2)
Example Burst Read	126	(4)
Treatment of Byte Enables During Read or Write	130	(3)
Byte Enables Presented on Entry to Data Phase	130	(1)
Byte Enables May Change In Each Data Phase	131	(1)
Data Phase with No Byte Enables Asserted	131	(1)
Target with Limited Byte Enable Support	132	(1)
Rule for Sampling of Byte Enables	132	(1)
Cases Where Byte Enables Can Be Ignored	133	(1)
Performance During Read Transactions	133	(2)
Write Transfers
Example Single Data Phase Write Transaction	135	(2)
Example Burst Write Transaction	137	(4)
Performance During Write Transactions	141	(2)
Memory and IO Addressing
Memory Addressing	143	(3)
The Start Address	143	(1)
Addressing Sequence During Memory Burst	143	(1)
Linear (Sequential) Mode	144	(1)
Cache Line Wrap Mode	144	(1)
When Target Doesn't Support Setting on AD[1:0]	145	(1)
PCI IO Addressing	146	(7)
Do Not Merge Processor IO Writes	146	(1)
General	146	(1)
Decode By Device That Owns Entire IO Dword	147	(1)
Decode by Device With 8-Bit or 16-Bit Ports	147	(1)
Unsupported Byte Enable Combination Results in Target Abort	148	(1)
Null First Data Phase Is Legal	149	(1)
IO Address Management	149	(1)
X86 Processor Cannot Perform IO Burst	149	(1)
Burst IO Address Counter Management	150	(1)
When IO Target Doesn't Support Multi-Data Phase Transactions	150	(1)
Legacy IO Decode	151	(1)
When Legacy IO Device Owns Entire Dword	151	(1)
When Legacy IO Device Doesn't Own Entire Dword	151	(2)
Fast Back-to-Back & Stepping
Fast Back-to-Back Transactions	153	(9)
Decision to Implement Fast Back-to-Back Capability	155	(1)
Scenario 1: Master Guarantees Lack of Contention	155	(1)
1st Must Be Write, 2nd Is Read or Write, But Same Target	155	(4)
How Collision Avoided On Signals Driven By Target	159	(1)
How Targets Recognize New Transaction Has Begun	159	(1)
Fast Back-to-Back and Master Abort	159	(1)
Scenario Two: Targets Guarantee Lack of Contention	160	(2)
Address/Data Stepping	162	(9)
Advantages: Diminished Current Drain and Crosstalk	162	(1)
Why Targets Don't Latch Address During Stepping Process	163	(1)
Data Stepping	163	(1)
How Device Indicates Ability to Use Stepping	163	(1)
Designer May Step Address, Data, PAR (and PAR64) and IDSEL	164	(1)
Continuous and Discrete Stepping	165	(1)
Disadvantages of Stepping	165	(1)
Preemption While Stepping in Progress	166	(1)
Broken Master	167	(1)
Stepping Example	167	(1)
When Not to Use Stepping	168	(1)
Who Must Support Stepping?	169	(2)
Early Transaction End
Introduction	171	(1)
Master-Initiated Termination	172	(8)
Master Preempted	172	(1)
Introduction	172	(1)
Preemption During Timeslice	173	(1)
Timeslice Expiration Followed by Preemption	174	(2)
Master Abort: Target Doesn't Claim Transaction	176	(1)
Introduction	176	(1)
Addressing Non-Existent Device	176	(1)
Normal Response To Special Cycle Transaction	176	(1)
Configuration Transaction Unclaimed	176	(1)
No Target Will Claim Transaction Using Reserved Command	177	(1)
Master Abort On Single vs. Multiple-Data Phase Transaction	177	(1)
Master Abort on Single Data Phase Transaction	177	(1)
Master Abort on Multi-Data Phase Transaction	178	(2)
Action Taken by Master in Response to Master Abort	180	(1)
General	180	(1)
Master Abort On Special Cycle Transaction	180	(1)
Master Abort On Configuration Access	180	(1)
Target-Initiated Termination	180	(18)
STOP# Signal Puts Target In the Driver's Seat	180	(1)
STOP# Not Permitted During Turn-Around Cycle	181	(1)
Disconnect	181	(1)
Resumption of Disconnected Transaction Is Optional	181	(1)
Reasons Target Issues Disconnect	181	(1)
Target Slow to Complete Subsequent Data Phase	181	(1)
Target Doesn't Support Burst Mode	182	(1)
Memory Target Doesn't Understand Addressing Sequence	182	(1)
Transfer Crosses Over Target's Address Boundary	183	(1)
Burst Memory Transfer Crosses Cache Line Boundary	183	(1)
Disconnect With Data Transfer (A and B)	184	(1)
Disconnect A	184	(1)
Disconnect B	184	(2)
Disconnect Without Data Transfer	186	(1)
Disconnect Without Data Transfer---Type 1	186	(1)
Disconnect Without Data Transfer---Type 2	187	(2)
Retry	189	(1)
Reasons Target Issues Retry	189	(1)
Target Very Slow to Complete First Data Phase	189	(1)
Snoop Hit on Modified Cache Line	190	(1)
Resource Busy	190	(1)
Bridge Locked	190	(1)
Description of Retry	190	(1)
Retry Issued and IRDY# Already Asserted	191	(1)
Retry Issued and IRDY# Not Yet Asserted	192	(2)
Target Abort	194	(1)
Description	194	(1)
Some Reasons Target Issues Target Abort	195	(1)
Broken Target	195	(1)
I/O Addressing Error	195	(1)
Address Phase Parity Error	195	(1)
Master Abort on Other Side of PCI-to-PCI Bridge	195	(1)
Master's Response to Target Abort	195	(1)
Target Abort Example	196	(1)
After Retry/Disconnect, Repeat Request ASAP	197	(1)
General	197	(1)
Behavior of Device Containing Multiple Masters	197	(1)
Target-Initiated Termination Summary	198	(1)
Error Detection and Handling
Status Bit Name Change	199	(1)
Introduction to PCI Parity	199	(2)
PERR# Signal	201	(1)
Data Parity	201	(13)
Data Parity Generation and Checking on Read	201	(1)
Introduction	201	(1)
Example Burst Read	202	(3)
Data Parity Generation and Checking on Write	205	(1)
Introduction	205	(1)
Example Burst Write	205	(4)
Data Parity Reporting	209	(1)
General	209	(1)
Master Can Choose Not To Assert PERR#	209	(1)
Parity Error During Read	209	(1)
Important Note Regarding Chipsets That Monitor PERR#	210	(1)
Parity Error During Write	210	(2)
Data Parity Error Recovery	212	(1)
Special Case: Data Parity Error During Special Cycle	213	(1)
Devices Excluded from PERR# Requirement	213	(1)
Chipsets	213	(1)
Devices That Don't Deal with OS/Application Program or Data	214	(1)
SERR# Signal	214	(7)
Address Phase Parity	215	(1)
Address Phase Parity Generation and Checking	215	(2)
Address Phase Parity Error Reporting	217	(1)
System Errors	218	(1)
General	218	(1)
Address Phase Parity Error	218	(1)
Data Parity Error During Special Cycle	218	(1)
Master of MSI Receives an Error	218	(1)
Target Abort Detection	219	(1)
Other Possible Causes of System Error	219	(1)
Devices Excluded from SERR# Requirement	219	(2)
Interrupts
Three Ways To Deliver Interrupts To Processor	221	(1)
Using Pins vs. Using MSI Capability	222	(1)
Single-Function PCI Device	222	(2)
Multi-Function PCI Device	224	(1)
Connection of INTx# Pins to System Board Traces	224	(1)
Interrupt Routing	225	(8)
General	225	(5)
Routing Recommendation In PCI Specification	230	(1)
BIOS ``Knows'' Interrupt Trace Layout	231	(1)
Well-Designed Chipset Has Programmable Interrupt Router	231	(1)
Interrupt Routing Information	232	(1)
Interrupt Routing Table	233	(5)
General	233	(1)
Finding the Table	234	(4)
PCI Interrupts Are Shareable	238	(1)
Hooking the Interrupt	239	(1)
Interrupt Chaining	239	(5)
General	239	(1)
Step 1: Initialize All Entries To Point To Dummy Handler	240	(1)
Step 2: Initialize All Entries For Embedded Devices	241	(1)
Step 3: Hook Entries For Embedded Device BIOS Routines	241	(1)
Step 4: Perform Expansion Bus ROM Scan	241	(1)
Step 5: Perform PCI Device Scan	242	(1)
Step 6: Load OS	243	(1)
Step 7: OS Loads and Call Drivers' Initialization Code	243	(1)
Linked-List Has Been Built for Each Interrupt Level	244	(1)
Servicing Shared Interrupts	244	(6)
Example Scenario	244	(2)
Both Devices Simultaneously Generate Requests	246	(1)
Processor Interrupted and Requests Vector	246	(3)
First Handler Executed	249	(1)
Jump to Next Driver in Linked List	249	(1)
Jump to Dummy Handler: Control Passed Back to Interrupted Program	249	(1)
Implied Priority Scheme	250	(1)
Interrupts and PCI-to-PCI Bridges	251	(1)
Message Signaled Interrupts (MSI)	252	(13)
Introduction	252	(1)
Advantages of MSI Interrupts	252	(1)
Basics of MSI Configuration	252	(2)
Basics of Generating an MSI Interrupt Request	254	(1)
How Is the Memory Write Treated by Bridges?	255	(1)
Memory Already Sync'd When Interrupt Handler Entered	256	(1)
The Problem	256	(1)
The Old Way of Solving the Problem	256	(1)
How MSI Solves the Problem	256	(1)
Interrupt Latency	257	(1)
MSI Are Non-Shared	257	(1)
MSI Is a New Capability Type	258	(1)
Description of the MSI Capability Register Set	259	(1)
Capability ID	259	(1)
Pointer to Next New Capability	259	(1)
Message Control Register	259	(2)
Message Address Register	261	(1)
Message Data Register	262	(1)
Message Write Can Have Bad Ending	262	(1)
Retry or Disconnect	262	(1)
Master or Target Abort Received	262	(1)
Write Results In Data Parity Error	263	(1)
Some Rules, Recommendations, etc	263	(2)
The 64-bit PCI Extension
64-bit Data Transfers and 64-bit Addressing: Separate Capabilities	265	(1)
64-Bit Extension Signals	266	(1)
64-bit Cards in 32-bit Add-in Connectors	266	(1)
Pullups Prevent 64-bit Extension from Floating When Not in Use	267	(3)
Problem: a 64-bit Card in a 32-bit PCI Connector	268	(1)
How 64-bit Card Determines Type of Slot Installed In	269	(1)
64-bit Data Transfer Capability	270	(17)
Only Memory Commands May Use 64-bit Transfers	271	(1)
Start Address Quadword-Aligned	271	(1)
64-bit Target's Interpretation of Address	272	(1)
32-bit Target's Interpretation of Address	272	(1)
64-bit Initiator and 64-bit Target	272	(4)
64-bit Initiator and 32-bit Target	276	(4)
Null Data Phase Example	280	(2)
32-bit Initiator and 64-bit Target	282	(1)
Performing One 64-bit Transfer	282	(1)
With 64-bit Target	283	(1)
With 32-bit Target	284	(1)
Simpler and Just as Fast: Use 32-bit Transfers	284	(1)
With Known 64-bit Target	284	(3)
Disconnect on Initial Data Phase	287	(1)
64-bit Addressing	287	(10)
Used to Address Memory Above 4GB	287	(1)
Introduction	288	(1)
64-bit Addressing Protocol	288	(1)
64-bit Addressing by 32-bit Initiator	288	(3)
64-bit Addressing by 64-bit Initiator	291	(4)
32-bit Initiator Addressing Above 4GB	295	(1)
Subtractive Decode Timing Affected	295	(1)
Master Abort Timing Affected	296	(1)
Address Stepping	296	(1)
FRAME# Timing in Single Data Phase Transaction	296	(1)
64-bit Parity	297	(2)
Address Phase Parity	297	(1)
PAR64 Not Used for Single Address Phase	297	(1)
PAR64 Not Used for Dual-Address Phases by 32-bit Master	297	(1)
PAR64 Used for DAC by 64-bit Master When Requesting 64-bit Transfers	297	(1)
Data Phase Parity	297	(2)
66MHz PCI Implementation
Introduction	299	(1)
66MHz Uses 3.3V Signaling Environment	299	(1)
How Components Indicate 66MHz Support	300	(3)
66MHz-Capable Status Bit	300	(1)
M66EN Signal	301	(1)
How Clock Generator Sets Its Frequency	301	(2)
Does Clock Have to be 66MHz?	303	(1)
Clock Signal Source and Routing	303	(1)
Stopping Clock and Changing Clock Frequency	303	(1)
How 66MHz Components Determine Bus Speed	303	(1)
System Board with Separate Buses	304	(1)
Maximum Achievable Throughput	305	(1)
Electrical Characteristics	305	(2)
Latency Rule	307	(1)
66MHz Component Recommended Pinout	307	(1)
Adding More Loads and/or Lengthening Bus	308	(1)
Number of Add-In Connectors	308	(1)
Intro to Configuration Address Space
Introduction	309	(1)
PCI Device vs. PCI Function	310	(1)
Three Address Spaces: I/O, Memory and Configuration	311	(3)
Host Bridge Needn't Implement Configuration Space	314	(1)
System with Single PCI Bus	314	(3)
Configuration Transactions
Who Performs Configuration?	317	(1)
Bus Hierarchy	318	(3)
Introduction	318	(1)
Case 1: Target Bus Is PCI Bus 0	319	(1)
Case 2: Target Bus Is Subordinate To Bus 0	319	(2)
Must Respond To Config Accesses Within 225 Clocks After RST#	321	(1)
Intro to Configuration Mechanisms	321	(1)
Configuration Mechanism #1 (The Only Mechanism!)	322	(8)
Background	323	(1)
Configuration Mechanism #1 Description	324	(1)
General	324	(1)
Configuration Address Port	325	(1)
Bus Compare and Data Port Usage	326	(1)
Single Host/PCI Bridge	327	(1)
Multiple Host/PCI Bridges	327	(2)
Software Generation of Special Cycles	329	(1)
Configuration Mechanism #2 (is obsolete)	330	(5)
Basic Configuration #2 Mechanism	331	(2)
Configuration Space Enable, or CSE, Register	333	(1)
Forward Register	333	(1)
Support for Peer Bridges on Host Bus	334	(1)
Generation of Special Cycles	334	(1)
PowerPC PReP Configuration Mechanism	335	(1)
Type 0 Configuration Transaction	335	(9)
Address Phase	335	(3)
Implementation of IDSEL	338	(1)
Method One---IDSELs Routed Over Unused AD Lines	338	(2)
Method Two---IDSEL Output Pins/Traces	340	(1)
Resistive-Coupling Means Stepping in Type 0 Transactions	341	(1)
Data Phase Entered, Decode Begins	341	(1)
Type 0 Configuration Transaction Examples	342	(2)
Type 1 Configuration Transactions	344	(4)
Description	344	(2)
Special Cycle Request	346	(2)
Target Device Doesn't Exist	348	(1)
Configuration Burst Transactions Permitted	349	(1)
64-Bit Configuration Transactions Not Permitted	350	(1)
Configuration Registers
Intro to Configuration Header Region	351	(3)
Mandatory Header Registers	354	(21)
Introduction	354	(1)
Registers Used to Identify Device's Driver	354	(1)
Vendor ID Register	354	(1)
Device ID Register	354	(1)
Subsystem Vendor ID and Subsystem ID Registers	355	(1)
Purpose of This Register Pair	355	(1)
Must Contain Valid Data When First Accessed	356	(1)
Revision ID Register	356	(1)
Class Code Register	356	(1)
General	356	(1)
Purpose of Class Code Register	356	(1)
Programming Interface Byte	357	(11)
Command Register	368	(3)
Status Register	371	(4)
Header Type Register	375	(1)
Other Header Registers	375	(15)
Introduction	375	(1)
Cache Line Size Register	376	(1)
Latency Timer: ``Timeslice'' Register	376	(1)
BIST Register	377	(1)
Base Address Registers (BARs)	378	(1)
Memory-Mapping Recommended	379	(1)
Memory Base Address Register	380	(1)
Decoder Width Field	380	(1)
Prefetchable Attribute Bit	380	(1)
Base Address Field	381	(1)
IO Base Address Register	382	(1)
Introduction	382	(1)
Description	382	(1)
PC-Compatible IO Decoder	382	(1)
Legacy IO Decoders	383	(1)
Determining Block Size and Assigning Address Range	384	(1)
How It Works	384	(1)
A Memory Example	384	(1)
An IO Example	385	(1)
Smallest/Largest Decoder Sizes	385	(1)
Smallest/Largest Memory Decoders	385	(1)
Smallest/Largest IO Decoders	385	(1)
Expansion ROM Base Address Register	386	(2)
CardBus CIS Pointer	388	(1)
Interrupt Pin Register	388	(1)
Interrupt Line Register	388	(1)
Min_Gnt Register: Timeslice Request	389	(1)
Max_Lat Register: Priority-Level Request	390	(1)
New Capabilities	390	(18)
Configuration Header Space Not Large Enough	390	(1)
Discovering That New Capabilities Exist	390	(3)
What the New Capabilities List Looks Like	393	(1)
AGP Capability	394	(1)
AGP Status Register	395	(1)
AGP Command Register	395	(2)
Vital Product Data (VPD) Capability	397	(1)
Introduction	397	(1)
It's Not Really Vital	398	(1)
What Is VPD?	398	(1)
Where Is the VPD Really Stored?	398	(1)
VPD On Cards vs. Embedded PCI Devices	398	(1)
How Is VPD Accessed?	398	(1)
Reading VPD Data	399	(1)
Writing VPD Data	399	(1)
Rules That Apply To Both Read and Writes	399	(1)
VPD Data Structure Made Up of Descriptors and Keywords	400	(2)
VPD Read-Only Descriptor (VPD-R) and Keywords	402	(2)
Is Read-Only Checksum Keyword Mandatory?	404	(1)
VPD Read/Write Descriptor (VPD-W) and Keywords	405	(1)
Example VPD List	406	(2)
User-Definable Features (UDF)	408	(3)
Expansion ROMs
ROM Purpose---Device Can Be Used In Boot Process	411	(1)
ROM Detection	412	(3)
ROM Shadowing Required	415	(1)
ROM Content	415	(9)
Multiple Code Images	415	(3)
Format of a Code Image	418	(1)
General	418	(1)
ROM Header Format	419	(1)
ROM Signature	420	(1)
Processor/Architecture Unique Data	420	(1)
Pointer to ROM Data Structure	421	(1)
ROM Data Structure Format	421	(2)
ROM Signature	423	(1)
Vendor ID field in ROM data structure	423	(1)
Device ID in ROM data structure	423	(1)
Pointer to Vital Product Data (VPD)	423	(1)
PCI Data Structure Length	423	(1)
PCI Data Structure Revision	423	(1)
Class Code	424	(1)
Image Length	424	(1)
Revision Level of Code/Data	424	(1)
Code Type	424	(1)
Indicator Byte	424	(1)
Execution of Initialization Code	424	(3)
Introduction to Open Firmware	427	(4)
Introduction	427	(1)
Universal Device Driver Format	428	(1)
Passing Resource List to Plug-and-Play OS	429	(1)
BIOS Calls Bus Enumerators For Different Bus Environments	429	(1)
BIOS Selects Boot Devices and Finds Drivers For Them	430	(1)
BIOS Boots Plug-and-Play OS and Passes Pointer To It	430	(1)
OS Locates and Loads Drivers and Calls Init Code In each	430	(1)
Vital Product Data (VPD)	431	(6)
Moved From ROM to Configuration Space in 2.2	431	(1)
VPD Implementation in 2.1 Spec	431	(1)
Data Structure	431	(6)
Add-in Cards and Connectors
Add-In Connectors	437	(12)
32-and 64-bit Connectors	437	(5)
32-bit Connector	442	(1)
Card Present Signals	443	(1)
REQ64# and ACK64#	444	(1)
64-bit Connector	445	(1)
3.3V and 5V Connectors	445	(1)
Universal Card	446	(1)
Shared Slot	446	(2)
Riser Card	448	(1)
Snoop Result Signals on Add-in Connector	449	(1)
PME# and 3.3Vaux	449	(1)
Add-In Cards	449	(6)
3.3V, 5V and Universal Cards	449	(1)
Long and Short Form Cards	449	(1)
Small PCI (SPCI)	450	(1)
Component Layout	450	(2)
Maintain Integrity of Boundary Scan Chain	452	(1)
Card Power Requirement	452	(1)
Maximum Card Trace Lengths	453	(1)
One Load per Shared Signal	453	(2)
Hot-Plug PCI
The Problem	455	(1)
The Solution	456	(1)
No Changes To Adapter Cards	456	(1)
Software Elements	456	(4)
General	456	(2)
System Start Up	458	(2)
Hardware Elements	460	(2)
General	460	(1)
Attention Indicator and Optional Slot State Indicator	461	(1)
Option---Power Fault Detector	462	(1)
Option---Tracking System Power Usage	462	(1)
Card Removal and Insertion Procedures	462	(4)
On and Off States	463	(1)
Definition of On and Off	463	(1)
Turning Slot On	463	(1)
Turning Slot Off	463	(1)
Basic Card Removal Procedure	464	(1)
Basic Card Insertion Procedure	465	(1)
Quiescing Card and Driver	466	(1)
General	466	(1)
Pausing a Driver (Optional)	466	(1)
Shared Interrupt Must Be Handled Correctly	467	(1)
Quiescing a Driver That Controls Multiple Devices	467	(1)
Quiescing a Failed Card	467	(1)
Driver's Initial Accesses To Card	467	(1)
Treatment of Device ROM	468	(1)
Who Configures the Card?	468	(1)
Efficient Use of Memory and/or IO Space	469	(1)
Slot Identification	469	(2)
Physical Slot ID	469	(1)
Logical Slot ID	470	(1)
PCI Bus Number, Device Number	470	(1)
Translating Slot IDs	470	(1)
Card Sets	471	(1)
The Primitives	472	(3)
Issues Related to PCI RST#	475	(1)
66MHz-Related Issues	476	(1)
Power-Related Issues	476	(3)
Slot Power Requirements	476	(1)
Card Connected to Device With Separate Power Source	477	(2)
Power Management
Power Management Abbreviated ``PM'' In This Chapter	479	(1)
PCI Bus PM Interface Specification---But First	479	(1)
A Power Management Primer	480	(17)
Basics of PC PM	480	(2)
OnNow Design Initiative Scheme Defines Overall PM	482	(1)
Goals	483	(1)
Current Platform Shortcomings	483	(1)
No Cooperation Among System Components	483	(1)
Add-on Components Do Not Participate In PM	483	(1)
Current PM Schemes Fail Purposes of OnNow Goals	483	(1)
Installing New Devices Still Too Hard	484	(1)
Apps Generally Assume System Fully On At All Times	484	(1)
System PM States	484	(1)
Device PM States	485	(1)
Definition of Device Context	486	(1)
General	486	(1)
PM Event (PME) Context	487	(1)
Device Class-Specific PM Specifications	488	(1)
Default Device Class Specification	488	(1)
Device Class-Specific PM Specifications	488	(1)
Power Management Policy Owner	489	(1)
General	489	(1)
In Windows OS Environment	489	(1)
PCI Power Management vs. ACPI	489	(1)
PCI Bus Driver Accesses PCI Configuration and PM Registers	489	(1)
ACPI Driver Controls Non-Standard Embedded Devices	489	(2)
Some Example Scenarios	491	(1)
Scenario---Restore Function To Powered Up State	492	(2)
Scenario---OS Wishes To Power Down Bus	494	(1)
Scenario---Setup a Function-Specific System WakeUp Event	495	(2)
PCI Bus PM Interface Specification	497	(42)
Legacy PCI Devices---No Standard PM Method	497	(1)
Device Support for PCI PM Optional	497	(1)
Discovering Function's PM Capability	497	(3)
Power Management---PCI Bus vs. PCI Function	500	(1)
Bridge---Originating Device for a Secondary PCI Bus	500	(1)
PCI Bus PM States	500	(3)
Bus PM State vs. PM State of the PCI Functions On the Bus	503	(2)
Bus PM State Transitions	505	(1)
Function PM States	505	(1)
D0 State---Full On	506	(1)
D0 Uninitialized	506	(1)
D0 Active	506	(1)
D1 State---Light Sleep	507	(2)
D2 State---Deep Sleep	509	(2)
D3---Full Off	511	(1)
D3Hot State	511	(2)
D3Cold State	513	(1)
Function PM State Transitions	514	(3)
Detailed Description of PM Registers	517	(1)
PM Capabilities (PMC) Register	518	(2)
PM Control/Status (PMCSR) Register	520	(4)
Data Register	524	(1)
Determining Presence of Data Register	524	(1)
Operation of the Data Register	525	(1)
Multi-Function Devices	525	(1)
PCI-to-PCI Bridge Power Data	525	(2)
PCI-to-PCI Bridge Support Extensions Register	527	(2)
Detailed Description of PM Events	529	(1)
Two New Pins---PME# and 3.3Vaux	529	(1)
What Is a PM Event?	529	(1)
Example Scenario	529	(3)
Rules Associated With PME#'s Implementation	532	(1)
Example PME# Circuit Design	533	(1)
3.3Vaux	534	(1)
Can a Card With No Power Generate PME#?	534	(1)
Maintaining PME Context in D3cold State	535	(1)
System May or May Not Supply 3.3Vaux	536	(1)
3.3Vaux System Board Requirements	536	(1)
3.3Vaux Card Requirements	537	(1)
Card 3.3Vaux Presence Detection	537	(1)
Problem: In B3 State, PCI RST# Signal Would Float	538	(1)
Solution	538	(1)
OS Power Management Function Calls	539	(1)
Get Capabilities Function Call	539	(1)
Set Power State Function Call	539	(1)
Get Power Status Function Call	539	(1)
BIOS/POST Responsibilities at Startup	539	(2)
PCI-to-PCI Bridge
Scaleable Bus Architecture	541	(1)
Terminology	542	(1)
Example Systems	543	(4)
Example One	543	(2)
Example Two	545	(2)
PCI-to-PCI Bridge: Traffic Director	547	(4)
Latency Rules	551	(1)
Configuration Registers	552	(41)
General	552	(2)
Header Type Register	554	(1)
Registers Related to Device ID	554	(1)
Introduction	554	(1)
Vendor ID Register	554	(1)
Device ID Register	555	(1)
Revision ID Register	555	(1)
Class Code Register	555	(1)
Bus Number Registers	556	(1)
Introduction	556	(1)
Primary Bus Number Register	556	(1)
Secondary Bus Number Register	556	(1)
Subordinate Bus Number Register	557	(1)
Command Registers	557	(1)
Introduction	557	(1)
Command Register	557	(3)
Bridge Control Register	560	(4)
Status Registers	564	(1)
Introduction	564	(1)
Status Register (Primary Bus)	564	(1)
Secondary Status Register	565	(1)
Introduction To Chassis/Slot Numbering Registers	566	(2)
Address Decode-Related Registers	568	(1)
Basic Transaction Filtering Mechanism	568	(1)
Bridge Memory, Register Set and Device ROM	569	(1)
Introduction	569	(1)
Base Address Registers	569	(1)
Expansion ROM Base Address Register	570	(1)
Bridge's IO Filter	570	(1)
Introduction	570	(1)
Bridge Doesn't Support Any IO Space Behind Bridge	571	(1)
Bridge Supports 64KB IO Space Behind Bridge	571	(4)
Bridge Supports 4GB IO Space Behind Bridge	575	(2)
Legacy ISA IO Decode Problem	577	(2)
Some ISA Drivers Use Alias Addresses To Talk To Card	579	(1)
Problem: ISA and PCI-to-PCI Bridges on Same PCI Bus	579	(2)
PCI IO Address Assignment	581	(1)
Effect of Setting the ISA Enable Bit	582	(1)
Bridge's Memory Filter	582	(1)
Introduction	582	(2)
Determining If Memory Is Prefetchable or Not	584	(1)
Supports 4GB Prefetchable Memory On Secondary Side	584	(4)
Supports > 4GB Prefetchable Memory On Secondary	588	(1)
Rules for Prefetchable Memory	588	(2)
Bridge's Memory-Mapped IO Filter	590	(1)
Cache Line Size Register	591	(1)
Latency Timer Registers	592	(1)
Introduction	592	(1)
Latency Timer Register (Primary Bus)	592	(1)
Secondary Latency Timer Register	592	(1)
BIST Register	592	(1)
Interrupt-Related Registers	593	(1)
Configuration Process	593	(23)
Introduction	593	(1)
Bus Number Assignment	594	(1)
Chassis and Slot Number Assignment	594	(1)
Problem: Adding/Removing Bridge Causes Buses to Be Renumbered	594	(1)
If Buses Added/Removed, Slot Labels Must Remain Correct	595	(1)
Definition of a Chassis	595	(1)
Chassis/Slot Numbering Registers	596	(1)
Introduction	596	(1)
Slot Number Register (read-only)	597	(1)
Chassis Number Register (read/write)	598	(1)
Some Rules	599	(1)
Three Examples	599	(1)
Example One	599	(3)
Example Two	602	(2)
Example Three	604	(2)
Address Space Allocation	606	(2)
IRQ Assignment	608	(1)
Display Configuration	608	(1)
There May Be Two Display Adapters	608	(1)
Identifying the Two Adapters	609	(1)
The Adapters May Be On Same or Different Buses	609	(1)
Solution	610	(2)
PCI-to-PCI Bridge State After Reset	612	(1)
Non-VGA Graphics Controller (aka GFX) After Reset	613	(1)
VGA Graphics Controller After Reset	613	(1)
Effects of Setting VGA's Palette Snoop Bit	613	(1)
Effects of Clearing GFX's Palette Snoop Bit	613	(1)
Effects of Bridge's VGA-Related Control Bits	614	(1)
Detecting and Configuring Adapters and Bridges	614	(2)
Configuration and Special Cycle Filter	616	(6)
Introduction	616	(3)
Special Cycle Transactions	619	(1)
Type 1 Configuration Transactions	620	(1)
Type 0 Configuration Access	620	(2)
Interrupt Acknowledge Handling	622	(1)
PCI-to-PCI Bridge With Subtractive Decode Feature	622	(1)
Reset	623	(1)
Arbitration	623	(1)
Interrupt Support	624	(2)
Devices That Use Interrupt Traces	624	(2)
Devices That Use MSI	626	(1)
Buffer Management	626	(3)
Handling of Memory Write and Invalidate Command	627	(1)
Rules Regarding Posted Write Buffer Usage	628	(1)
Multiple-Data Phase Special Cycle Requests	628	(1)
Error Detection and Handling	629	(20)
General	629	(1)
Handling Address Phase Parity Errors	630	(1)
Introduction	630	(1)
Address Phase Parity Error on Primary Side	630	(1)
Address Phase Parity Error on Secondary Side	630	(1)
Read Data Phase Parity Error	631	(1)
Introduction	631	(1)
Parity Error When Performing Read on Destination Bus	631	(1)
Parity Error When Delivering Read Data To Originating Master	632	(1)
Bad Parity On Prefetched Data	632	(1)
Write Data Phase Parity Error	633	(1)
General	633	(2)
Data Phase Parity Error on IO or Configuration Write	635	(1)
Introduction	635	(1)
Master Request Error	635	(1)
Target Completion Error	636	(1)
Parity Error On a Subsequent Retry	637	(1)
Data Phase Parity Error on Posted Write	638	(1)
Introduction	638	(1)
Originating Bus Error---Pass It Along To Target	639	(1)
Destination Bus Error	640	(1)
Handling Master Abort	641	(2)
Handling Target Abort	643	(1)
Introduction	643	(1)
Target Abort On Delayed Write Transaction	644	(1)
Target Abort On Posted Write	644	(1)
Discard Timer Timeout	644	(3)
Handling SERR# on Secondary Side	647	(2)
Transaction Ordering & Deadlocks
Definition of Simple Device vs. a Bridge	649	(1)
Simple Device	649	(1)
Bridge	650	(1)
Simple Devices: Ordering Rules and Deadlocks	650	(2)
Ordering Rules For Simple Devices	650	(1)
Deadlocks Associated With Simple Devices	651	(1)
Scenario One	651	(1)
Scenario Two	651	(1)
Bridges: Ordering Rules and Deadlocks	652	(21)
Introduction	652	(1)
Bridge Manages Bi-Directional Traffic Flow	653	(1)
Producer/Consumer Model	654	(4)
General Ordering Requirements	658	(1)
Only Memory Writes Posted	658	(1)
Posted Memory Writes Always Complete In Order	658	(1)
Writes Moving In Opposite Directions Have No Relationship	659	(1)
Before Read Crosses Bridge, Memory Must Be Sync'd Up	659	(1)
Posted Write Acceptance Cannot Depend On Master Completion	659	(1)
Description	659	(1)
Exception To the Rule---Master Has Locked Target	660	(1)
Delayed Transaction Ordering Requirements	660	(1)
Bridge Ordering Rules	661	(1)
Rule 1---Ensures Posted Memory Writes Are Strongly-Ordered	662	(1)
Rule 2---Ensures Just-Latched Read Obtains Correct Data	662	(1)
Rule 3---Ensures DWR Not Done Until All Posted Writes Done	662	(1)
Rule 4---Bi-Directional Posted Writes Done Before Read Data Obtained	663	(1)
Rule 5---Avoids Deadlock Between Old and New Bridges	663	(3)
Rule 6---Avoids Deadlock Between New Bridges	666	(1)
Rule 7---Avoids Deadlock Between Old and New Bridges	667	(3)
Locking, Delayed Transactions and Posted Writes	670	(1)
Lock Passage Is Uni-Directional (Downstream-Only)	670	(1)
Once Locked, Bridge Only Permits Locking Master Access	670	(1)
Actions Taken Before Allowing Lock To Traverse Bridge	670	(1)
After Bridge Locked But Before Secondary Target Locked	671	(1)
After Secondary Target Locked, No Secondary Side Posting	671	(1)
Simplest Design---Bridge Reserved For Locking Master's Use	671	(2)
The PCI BIOS
Purpose of PCI BIOS	673	(1)
OS Environments Supported	674	(4)
General	674	(1)
Real-Mode	675	(1)
286 Protected Mode (16:16)	676	(1)
386 Protected Mode (16:32)	676	(1)
Today's OSs Use Flat Mode (0:32)	677	(1)
Determining if System Implements 32-bit BIOS	678	(1)
Determining Services 32-bit BIOS Supports	679	(1)
Determining if 32-bit BIOS Supports PCI BIOS Services	679	(1)
Calling PCI BIOS	680	(1)
PCI BIOS Present Call	680	(3)
Locking
Spec Redefined Lock Usage	683	(1)
Scenarios That Require Locking	684	(3)
General	684	(1)
EISA Master Initiates Locked Transaction Series Targeting Main Memory	684	(1)
Processor Initiates Locked Transaction Series Targeting EISA Memory	685	(1)
Possible Deadlock Scenario	685	(2)
PCI Solutions: Bus and Resource Locking	687	(9)
LOCK# Signal	687	(1)
Bus Lock: Permissible but Not Preferred	688	(1)
Resource Lock: Preferred Solution	689	(1)
Introduction	689	(1)
Determining Lock Mechanism Availability	689	(1)
Establishing Lock	690	(2)
Locked Bridge Cannot Accept Accesses From Either Side	692	(1)
Unlocked Targets May Be Accessed by any Master On Same PCI Bus	692	(1)
Access to Locked Target by Master Other than Owner: Retry	693	(1)
Continuation and/or End of Locked Transaction Series	694	(2)
Use of LOCK# with 64-bit Addressing	696	(1)
Locking and Delayed Transactions	696	(1)
Summary of Locking Rules	697	(2)
Implementation Rules for Masters	697	(1)
Implementation Rules for Targets	697	(2)
CompactPCI and PMC
Why CompactPCI?	699	(1)
CompactPCI Cards are PCI-Compatible	700	(1)
Basic PCI/CompactPCI Comparison	700	(1)
Basic Definitions	701	(11)
Standard PCI Environment	701	(1)
Passive Backplane	702	(3)
Compatibility Glyphs	705	(1)
Definition of a Bus Segment	705	(1)
Physical Slot Numbering	705	(1)
Logical Slot Numbering	705	(1)
Connector Basics	706	(1)
Introduction to Front and Rear-Panel IO	707	(1)
Front-Panel IO	707	(1)
Rear-Panel IO	708	(1)
Introduction to CompactPCI Cards	708	(2)
System Card	710	(1)
General	710	(1)
32-bit System Card	711	(1)
64-bit System Card	711	(1)
ISA Bus Bridge	711	(1)
Peripheral Cards	711	(1)
32-bit Peripheral Cards	711	(1)
64-bit Peripheral Card	711	(1)
Design Rules	712	(39)
Connectors	712	(1)
General	712	(1)
Pin Numbering (IEC 1076 versus CompactPCI)	712	(1)
Connector Keying	713	(1)
5V and 3.3V Cards	713	(1)
Universal Cards	714	(1)
32-bit PCI Pinout (J1/P1)	714	(2)
64-bit PCI Pinout (J2/P2)	716	(2)
Rear-Panel IO Pinouts	718	(1)
System and Peripheral Card Design Rules	719	(1)
Card Form Factors	719	(1)
General	719	(1)
3U Cards	719	(2)
6U Cards	721	(2)
Non-PCI Signals	723	(1)
System Card Implementation of IDSELs	724	(1)
Resistors Required on a Card	724	(1)
Series Resistors Required at the Connector Pin	724	(2)
Resistor Required at Peripheral Card's REQ# Driver Pin	726	(1)
Resistor Required at Each System Card Clock Driver Pin	726	(1)
Resistor Required at System Card's GNT# Driver Pin	726	(1)
Placement of Pull-Ups on System Card	726	(1)
System Card Pull-Ups Required on REQ64# and ACK64#	726	(1)
Bus Master Requires Pull-Up on GNT#	726	(1)
Decoupling Requirements	727	(1)
Peripheral Card Signal Stub Lengths	727	(1)
32-bit and 64-bit Stub Lengths	727	(1)
Clock Stub Length	727	(1)
System Card Stub Lengths	727	(1)
32-bit and 64-bit Stub Lengths	727	(1)
Clock Routing	727	(1)
Signal Loading	728	(1)
Peripheral Card Signal Loading	728	(1)
System Card Signal Loading	728	(1)
Card Characteristic Impedance	728	(1)
Connector Shielding	728	(1)
Front Panel and Front Panel IO Connectors	728	(1)
Backplane Design Rules	729	(1)
General	729	(1)
3U Backplane	730	(1)
6U Backplane	730	(4)
Dimensions	734	(1)
Overall Backplane Width	734	(1)
Overall Backplane Height	734	(1)
Connector Keying	734	(1)
System Slot Connector Population	734	(1)
Peripheral Slot Connector Population	734	(1)
Power Distribution	735	(1)
Power Specifications	735	(1)
Power Connections	735	(1)
DEG# and FAL# Interconnect	736	(1)
Power Decoupling	736	(3)
Signaling Environment	739	(1)
Clock Routing	739	(1)
8-Slot Backplane	739	(1)
7-Slot Backplane	740	(1)
Backplane with Six or Fewer Slots	740	(1)
Characteristic Impedance	741	(1)
8-Slot Termination	741	(1)
IDSEL Routing	741	(1)
Background	741	(1)
Backplane AD/IDSEL Interconnect	742	(1)
REQ#/GNT# Routing	743	(1)
Interrupt Line Routing	744	(1)
Backplane Routing of PCI Interrupt Request Lines	744	(1)
Backplane Routing of Legacy IDE Interrupt Request Lines	744	(1)
Non-PCI Signals	745	(1)
Geographical Addressing	745	(2)
Backplane 64-bit Support	747	(1)
Treatment of SYSEN# Signal	747	(1)
Treatment of M66EN Signal	747	(1)
Rear-Panel IO Transition Boards	748	(1)
Dimensions	748	(1)
Connectors Used for Rear-Panel IO	748	(1)
Other Mechanical Issues	748	(1)
Orientation Relative to Front-Panel CompactPCI Cards	748	(1)
Connector Pin Labeling	749	(1)
Connector P2 Rear-Panel IO Pinout	749	(2)
Hot Swap Capability	751	(3)
ENUM# Signal Added In CompactPCI 2.1 Spec	751	(1)
Electrical Insertion/Removal Occurs in Stages	752	(1)
Card Insertion Sequence	752	(1)
Card Removal Sequence	752	(1)
Separate Clock Lines Required	752	(1)
Three Levels of Implementation	753	(1)
Basic Hot-Swap	753	(1)
Installing a New Card	753	(1)
Removing a Card	753	(1)
Full Hot-Swap	754	(1)
High-Availability Hot-Swap	754	(1)
Telecom-Related Issues Regarding Connector Keying	754	(1)
PCI Mezzanine Cards (PMC)	754	(7)
Small Size Permits Attachment to CompactPCI Card	754	(1)
Specifications	755	(1)
Stacking Height and Card Thickness	755	(1)
PMC Card's Connector Area	755	(1)
Front-Panel Bezel	756	(1)
The PMC Connector	756	(1)
Mapping PMC Rear-Panel IO to 3U Rear-Panel IO	757	(1)
Mapping PMC Rear-Panel IO to 6U Rear-Panel IO	758	(3)
Appendix A---Glossary of Terms	761