Power Aware Design Methodologies

by Pedram, Massoud; Rabaey, Jan M.

• ISBN13: 9781402071522
• ISBN10: 1402071523
• Format: Hardcover
• Copyright: 2002-06-01
• Publisher: Kluwer Academic Pub

Summary

Power Aware Design Methodologies is on power-awareness in design. The difference between low-power design and power-awareness in design is that whereas low-power design refers to minimizing power with or without a performance constraint, power-aware design refers to maximizing some other performance metric, subject to a power budget (even while reducing power dissipation). Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control. The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful to the circuit and system designers, tool developers, and academic researchers and students. Power Aware Design Methodologies is written for the design professional and can be used as a textbook for an advanced course on power-aware design methodologies.

Table of Contents

Contributors	xvii
Preface	xix
Introduction	1	(8)
Massoud Pedram
Jan Rabaey
Introduction	1	(1)
Sources of Power Consumption	2	(1)
Low-Power Versus Power-Aware Design	2	(1)
Power Reduction Mechanisms in CMOS Circuits	3	(1)
Power Reduction Techniques in Microelectronic Systems	4	(1)
Book Organization and Overview	5	(2)
Summary	7	(2)
CMOS Device Technology Trends for Power-Constrained Applications	9	(42)
David J. Frank
Introduction	9	(2)
CMOS Technology Summary	11	(4)
Current CMOS Device Technology	11	(2)
ITRS Projections	13	(2)
Scaling Principles and Difficulties	15	(14)
General Scaling	16	(2)
Characteristic Scale Length	18	(2)
Limits to Scaling	20	(1)
Tunnelling Through the Gate Insulator	21	(2)
Junction Tunnelling	23	(1)
Discrete Doping Effects	24	(2)
Thermodynamic Effects	26	(3)
Power-constained Scaling Limits	29	(6)
Optimizing VDD and VT	29	(1)
Optimizing Gate Insulator Thickness and Gate Length - the Optimal End to Scaling	30	(3)
Discussion of the Optimizations	33	(2)
Exploratory Technology	35	(10)
Body- or Back Gate Bias	35	(1)
Strained Si	36	(2)
Fully-Depleted SOI	38	(2)
Double-gate FET Structures	40	(4)
Low Temperature Operation for High Performance	44	(1)
Summary	45	(6)
Low Power Memory Design	51	(40)
Yukihito Oowaki
Tohru Tanzawa
Introduction	51	(1)
Flash Memories	52	(22)
Flash Memory Cell Operation and Control Schemes	55	(1)
NOR Flash Memory	55	(4)
NAND Flash Memory	59	(4)
Circuits Used in Flash Memories	63	(1)
Charge Pump Circuits	64	(4)
Level Shifter	68	(3)
Sense Amplifier	71	(2)
Effect of the Supply Voltage Reduction on Power	73	(1)
Ferroelectronic memory	74	(8)
Basic Operation of FeRAM	74	(3)
Low Voltage FeRAM Design	77	(1)
Optimization of Bit-line Capacitance	77	(1)
Cell Plate Line Drive Techniques	77	(2)
Non-driven Cell Plate Line Scheme	79	(2)
Other Low Voltage Techniques	81	(1)
Embedded DRAM	82	(3)
Advantages of Embedded DRAM	82	(1)
Low Voltage Embedded DRAM Design	83	(2)
Summary	85	(6)
Low-Power Digital Circuit Design	91	(30)
Tadahiro Kuroda
Introduction	91	(1)
Low Voltage Technologies	92	(18)
Variable VDD and VT	93	(3)
Dual VDD's	96	(2)
Multiple VDD's and VT's	98	(1)
Multiple Power Supplies	98	(3)
Multiple Threshold Voltages	101	(3)
Multiple Transistor Width	104	(2)
Summary	106	(1)
Low Voltage SRAM	106	(4)
Low Switching - Activity Techniques	110	(8)
Low Capacitance Technologies	118	(1)
Summary	118	(3)
Low Voltage Analog Design	121	(30)
K. Uyttenhove
M. Steyaert
Introduction	122	(4)
Fundamental Limits to Low Power Consumption	122	(1)
Practical Limitations for Achieving the Minimum Power Consumption	123	(1)
Implications of Reduced Supply Voltage	124	(2)
Speed-power-accuracy Trade-off in High, Speed ADC's	126	(10)
High-speed ADC Architecture	126	(3)
Models for Matching in Deep-submicron Technologies	129	(1)
What is Transistor Mismatch?	129	(1)
Transistor Mismatch Modelling	130	(4)
Speed-power-accuracy Trade-off	134	(2)
Impact of Voltage Scaling on Trade-off in High-Speed ADC's	136	(9)
Slew Rate Dominated Circuits vs. Settling Time Dominated Circuits	143	(2)
Solutions for Low Voltage ADC Design	145	(2)
Technological Modifications	145	(1)
System Level	146	(1)
Architectural Level	146	(1)
Comparison with Published ADC's	147	(1)
Summary	148	(3)
Low Power Flip - Flop and Clock Network Design Methodologies in High - Performance System-On-A-Chip	151	(30)
Chulwoo Kim
Sung-Mo (Steve) Kang
Introduction	151	(4)
Power Consumption in VLSI Chips	151	(1)
Power Consumption of Clocking System in VLSI Chips	152	(3)
High - Performance Flip - Flops	155	(1)
Low-Power Flip - Flops	156	(15)
Master-Slave Latch Pairs	157	(1)
Statistical Power Reduction Flip - Flops	158	(2)
Small Swing Flip - Flops	160	(2)
Double-Edge Triggered Flip - Flops	162	(3)
Low-Swing Clock Double-Edge Triggered Flip - Flop	165	(5)
Comparisons of Simulation Results	170	(1)
More on Clocking Power-Saving Methodologies	171	(3)
Clock Gating	172	(1)
Embedded Logic in Flip - Flops	173	(1)
Clock Buffer (Repeater) and Tree Design	173	(1)
Potential Issues in Multi-GHz SoCs in VDSM Technology	174	(1)
Comparison of Power-Saving Approaches	174	(2)
Summary	176	(5)
Power Optimization by Datapath Width Adjustment	181	(20)
Hiroto Yasuura
Hiroyuki Tomiyama
Introduction	181	(2)
Power Consumption and Datapath Width	183	(4)
Datapath Width and Area	183	(2)
Energy Consumption and Datapath Width	185	(1)
Dynamic Adjustment of Datapath Width	186	(1)
Bit-Width Analysis	187	(1)
Datapath Width Adjustment on a Soft-Core Processor	188	(5)
Case Studies	193	(3)
ADPCM Decoder LSI	193	(1)
MPEG-2 AAC Decoder	194	(1)
MPEG-2 Video Decoder Processors	195	(1)
Quality-Driven Design	196	(2)
Summary	198	(3)
Energy-Efficient Design of High-Speed Links	201	(40)
Gu-Yeon Wei
Mark Horowitz
Aeka Kim
Introduction	201	(2)
Overview of Link Design	203	(12)
Figures of Merit	204	(2)
Transmitter	206	(1)
High-impedance Drivers	206	(1)
Single-ended vs. Differential	207	(2)
Slew-rate Control	209	(1)
Receiver	210	(2)
Clock Synthesis and Timing Recovery	212	(2)
Putting It Together	214	(1)
Approaches for Energy Efficiency	215	(7)
Parallelism	215	(1)
Sub-clock Period Symbols	216	(2)
Pulse-amplitude Modulation	218	(1)
Adaptive Power Supply Regulation	218	(4)
Putting It Together	222	(1)
Examples	222	(14)
Supply-Regulated PLL and DLL Design	223	(1)
DLL	223	(3)
PLL design	226	(2)
Adaptive-Supply Serial Links	228	(1)
Multi-phase Clock Generation	229	(1)
Low-voltage Transmitter and Receiver	230	(1)
Clock-recovery PLL	231	(1)
Low-Power Area-Efficient Hi-Speed I/O Circuit Techniques	232	(2)
Transmitter	234	(1)
Receiver	234	(1)
Putting It Together	235	(1)
Summary	236	(5)
System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing	241	(36)
Diana Marculescu
Radu Marculescu
Introduction	241	(1)
System-Level Modeling and Design Exploration	242	(3)
The SAN Modeling Paradigm	245	(4)
The SAN Model Construction	246	(2)
Performance Model Evaluation	248	(1)
Case Study: Power-Performance of the MPEG-2 Video Decoder Application	249	(4)
System Specification	249	(1)
Application Modeling	250	(1)
Platform Modeling	251	(1)
Mapping	252	(1)
Results and Discussion	253	(4)
Performance Results	254	(2)
Power Results	256	(1)
Microarchitecture-level Power Modeling	257	(4)
Efficient Processor Design Exploration for Low Power	261	(7)
Efficient Microarchitectural Power Simulation	262	(3)
Design Exploration Trade-off	265	(3)
Implications of Application Profile on Energy-aware Computing	268	(5)
On-the-fly Energy Optimal Configuration Detection and Optimization	269	(1)
Energy Profiling in Hardware	269	(1)
On-the-fly Optimization of the Processor Configuration	270	(1)
Selective Dynamic Voltage Scaling	270	(1)
Effectiveness of Microarchitecture Resource Scaling	271	(1)
Comparison with Static Throttling Methods	272	(1)
Summary	273	(4)
Tools and Techniques for Integrated Hardware-Software Energy Optimizations	277	(20)
N. Vijaykrishnan
M. Kandemeir
A. Sivasubramaniam
M. J. Irwin
Introduction	277	(2)
Power Modeling	279	(2)
Design of Simulators	281	(5)
A SimOS Based Energy Simulator	282	(2)
Trimaran-based VLIW Energy Simulator	284	(2)
Hardware-Software Optimizations: Case Studies	286	(6)
Studying the Impact of Kernel and Peripheral Energy Consumption	286	(3)
Studying the Impact of Compiler Optimizations	289	(1)
Superblock	289	(1)
Hyperblock	289	(2)
Studying the Impact of Architecture Optimizations	291	(1)
Summary	292	(5)
Power-Aware Communication Systems	297	(38)
Mani Srivastava
Introduction	298	(1)
Where Does the Energy Go in Wireless Communications	299	(5)
Electronic and RF Energy Consumption in Radios	299	(3)
First-order Energy Model for Wireless Communication	302	(1)
Power consumption in Short-range Radios	302	(2)
Power Reduction and Management for Wireless Communications	304	(1)
Lower Layer Techniques	305	(14)
Dynamic Power Management of Radios	305	(1)
The Energy-speed Control Knobs	306	(4)
Exploiting the Radio-level Energy-speed Control knobs in the Energy-aware Packet Scheduling	310	(5)
More Lower-layer Energy-speed Control Knobs	315	(1)
Frame Length Adaptation	316	(1)
Energy-aware Medium Access Control	317	(2)
Higher Layer Techniques	319	(13)
Network Topology Management	319	(2)
Topology Management via Energy vs. Density Tradeoff	321	(3)
Topology Management via Energy vs. Set-up Latency Trade-off	324	(5)
Hybrid Approach	329	(1)
Energy-aware Data Routing	329	(3)
Summary	332	(3)
Power Aware Wireless Microsensor Networks	335	(38)
Rex Min
Seong-Hwan Cho
Manish Bhardwaj
Eugene Shih
Alice Wang
Anantha Chandrakasan
Introduction	335	(3)
Node Energy Consumption Characteristics	338	(5)
Hardware Architecture	338	(1)
Digital Processing Energy	339	(2)
Radio Transceiver Energy	341	(2)
Power Awareness Through Energy Scalability	343	(12)
Dynamic Voltage Scaling	343	(2)
Ensembles of Systems	345	(1)
Variable Radio Modulation	346	(3)
Adaptive Forward Error Correction	349	(6)
Power-Aware Communication	355	(10)
Low-Power Media Access Control Protocol	355	(4)
Minimum Energy Multihop Forwarding	359	(2)
Clustering and Aggregation	361	(2)
Distributed Processing through System Partitioning	363	(2)
Node Prototyping	365	(4)
Hardware Architecture	366	(3)
Measured Energy Consumption	369	(1)
Future Directions	369	(1)
Summary	370	(3)
Circuit and System Level Power Management	373	(40)
Farzan Fallah
Massoud Pedram
Introduction	373	(4)
System-Level Power Management Techniques	377	(9)
Greedy Policy	377	(1)
Fixed Time-out Policy	378	(1)
Predictive Shut-down Policy	378	(1)
Predictive Wake-up Policy	379	(1)
Stochastic Methods	379	(1)
Modeling and Optimization Framework	380	(1)
A Detailed Example	381	(4)
Adaptive Power Control	385	(1)
Battery-aware Power Management	386	(1)
Component-Level Power Management Techniques	386	(22)
Dynamic Power Minimization	387	(1)
Clock Gating	388	(4)
Dynamic Voltage and Frequency Scaling	392	(4)
Pre-computation	396	(2)
Leakage Power Minimization	398	(3)
Power Gating	401	(3)
Body Bias Control	404	(1)
Minimum Leakage Vector Method	405	(3)
Summary	408	(5)
Tools and Methodologies for Power Sensitive Design	413	(38)
Jerry Frenkil
Introduction	413	(1)
The Design Automation View	414	(13)
Power Consumption Components	415	(2)
Different Types of Power Tools	417	(1)
Power Tool Data Requirements	418	(1)
Design Data	419	(1)
Environmental Data	419	(2)
Technology Data & Power Models	421	(2)
Modeling Standards	423	(3)
Different Types of Power Measurements	426	(1)
Power Dissipation and Power Consumption	426	(1)
Instantaneous Power	426	(1)
RMS Power	427	(1)
Time Averaged Power	427	(1)
Translator Level Tools	427	(4)
Transistor Level Analysis Tools	428	(1)
Transistor Level Optimization Tools	428	(1)
Transistor Level Characterization and Modeling Tools	429	(1)
Derivative Transistor Level Tools	430	(1)
Gate-Level Tools	431	(6)
Gate-Level Analysis Tools	432	(1)
Gate-Level Optimization Tools	432	(3)
Gate-Level Modeling Tools	435	(1)
Derivative Gate-Level Tools	436	(1)
Register Transfer-level Tools	437	(3)
RTL Analysis Tools	438	(2)
RTL Optimization Tools	440	(1)
Behavior-Level Tools	440	(2)
Behavior Level Analysis Tools	441	(1)
Behavior Level Optimization Tools	442	(1)
System-Level Tools	442	(1)
A Power-Sensitive Design Methodology	443	(4)
Power Sensitive Design	444	(1)
Feedback vs. Feed Forward	444	(3)
A View to the Future	447	(1)
Summary	447	(4)
Reconfigurable Processors - The Road to Flexible Power-Aware Computing	451	(22)
J. Rabaey
A. Abnous
H. Zhang
M. Wan
V. George
V. Prabhu
Introduction	451	(1)
Platform-Based Design	452	(2)
Opportunities for Energy Minimization	454	(2)
Voltage as a Design Variable	455	(1)
Eliminating Architectural Waste	455	(1)
Programmable Architectures-An Overview	456	(6)
Architecture Models	457	(3)
Homogeneous and Heterogeneous Architectures	460	(1)
Agile Computing Systems (Heterogeneous Compute Systems-on-a-chip)	461	(1)
The Berkeley Pleiades Platform [10]	462	(7)
Concept	462	(1)
Architecture	463	(2)
Communication Network	465	(1)
Benchmark Example: The Maia Chip [10]	466	(3)
Architectural Innovations Enable Circuit-Level Optimizations	469	(2)
Dynamic Voltage Scaling	469	(1)
Reconfigurable Low-swing Interconnect Network	470	(1)
Summary	471	(2)
Energy-Efficient System-Level Design	473	(44)
Luca Benini
Giovanni De Micheli
Introduction	473	(1)
Systems on Chips and Their Design	474	(3)
SOC Case Studies	477	(7)
Emotion Engine	477	(2)
MPEG4 Core	479	(3)
Single-chip Voice Recorder	482	(2)
Design of Memory Systems	484	(7)
On-chip Memory Hierarchy	485	(2)
Explorative Techniques	487	(1)
Memory Partitioning	488	(1)
Extending the Memory Hierarchy	489	(1)
Bandwidth Optimization	490	(1)
Design of Interconnect Networks	491	(7)
Signal Transmission on Chip	492	(1)
Network Architectures and Control Protocols	493	(1)
Energy-efficient Design: Techniques and Examples	494	(1)
Physical Layer	495	(1)
Data-link Layer	495	(2)
Network Layer	497	(1)
Transport Layer	498	(1)
Software	498	(12)
System Software	499	(1)
Dynamic Power Management	500	(2)
Information-flow Management	502	(1)
Application Software	502	(2)
Software Synthesis	504	(4)
Software Compilation	508	(2)
Application Software and Power Management	510	(1)
Summary	510	(7)
Index	517