Principles of Testing Electronic Systems

by Mourad, Samiha; Zorian, Yervant

• ISBN13: 9780471319313
• ISBN10: 0471319317
• Edition: 1st
• Format: Hardcover
• Copyright: 2000-07-25
• Publisher: Wiley-Interscience

Summary

A pragmatic approach to testing electronic systems As we move ahead in the electronic age, rapid changes in technology pose an ever-increasing number of challenges in testing electronic products. Many practicing engineers are involved in this arena, but few have a chance to study the field in a systematic way-learning takes place on the job. By covering the fundamental disciplines in detail, Principles of Testing Electronic Systems provides design engineers with the much-needed knowledge base. Divided into five major parts, this highly useful reference relates design and tests to the development of reliable electronic products; shows the main vehicles for design verification; examines designs that facilitate testing; and investigates how testing is applied to random logic, memories, FPGAs, and microprocessors. Finally, the last part offers coverage of advanced test solutions for today's very deep submicron designs. The authors take a phenomenological approach to the subject matter while providing readers with plenty of opportunities to explore the foundation in detail. Special features include: * An explanation of where a test belongs in the design flow * Detailed discussion of scan-path and ordering of scan-chains * BIST solutions for embedded logic and memory blocks * Test methodologies for FPGAs * A chapter on testing system on a chip * Numerous references

Author Biography

<b>SAMIHA MOURAD, PhD</b>, is Professor of Electrical Engineering at Santa Clara University, Santa Clara, California. <b>YERVANT ZORIAN, PhD</b>, is Chief Technology Advisor at Logic Vision, Inc., San Jose, California.

Table of Contents

Preface	xv
PART I DESIGN AND TEST	1	(106)
Overview of Testing	3	(24)
Reliability and Testing	3	(1)
Design Process	4	(2)
Verification	6	(2)
Functional Simulation	7	(1)
Timing Simulation	8	(1)
Testing	8	(2)
Faults and Their Detection	10	(2)
Test Pattern Generation	12	(1)
Fault Coverage	13	(1)
Types of Tests	13	(2)
Exhaustive Tests	13	(1)
Pseudoexhaustive Tests	13	(1)
Pseudorandom Tests	14	(1)
Deterministic Tests	15	(1)
Test Application	15	(3)
On-Line Versus Off-Line Tests	16	(1)
Automatic Test Equipment	16	(1)
On-Chip Versus Off-Chip Testing	17	(1)
Design for Test	18	(1)
Controllability	18	(1)
Observability	19	(1)
Testing Economics	19	(3)
Yield and Defect Level	20	(1)
Fault Coverage and Defect Level	21	(1)
To Explore Further	22	(5)
References	22	(2)
Problems	24	(3)
Defects, Failures, and Faults	27	(30)
Introduction	27	(2)
Physical Defects	29	(2)
Extra and Missing Material	30	(1)
Oxide Breakdown	30	(1)
Electromigration	30	(1)
Failures Modes	31	(1)
Opens	31	(1)
Shorts	32	(1)
Faults	32	(1)
Stuck-at Faults	33	(3)
Single Stuck-at Faults	33	(2)
Multiple Stuck at Faults	35	(1)
Fault Lists	36	(3)
Equivalence Relation	37	(1)
Dominance Relation	37	(1)
Fault Collapsing	37	(2)
Bridging Faults	39	(2)
Shorts and Opens Faults	41	(4)
NMOS Circuits	42	(1)
CMOS Circuits	43	(2)
Delay Faults	45	(3)
Temporary Failures	48	(2)
Transient Faults	48	(2)
Intermittent Faults	50	(1)
Noise Failures	50	(7)
References	51	(3)
Problems	54	(3)
Design Representation	57	(24)
Levels of Abstraction	57	(2)
Mathematical Equations	59	(7)
Switching Functions	59	(2)
Boolean Difference	61	(1)
Finite State Machines	62	(1)
Transistor-Level Representation	63	(3)
Tabular Format	66	(1)
Truth Tables	66	(1)
State Tables	66	(1)
Graphical Representation	67	(1)
Graphs	68	(2)
Binary Decision Diagrams	70	(3)
Netlists	73	(2)
Hardware Description Languages	75	(6)
Verilog Language	76	(1)
VHDL Language	77	(1)
References	78	(1)
Problems	79	(2)
VLSI Design Flow	81	(26)
Introduction	81	(1)
CAD Tools	82	(1)
Algorithms	83	(2)
Synthesis	85	(5)
Behavioral Synthesis	88	(1)
Logic Synthesis	89	(1)
Design Methodologies	90	(2)
Semicustom Design	92	(4)
Standard Cell Design	92	(1)
Mask-Programmable Gate Arrays	92	(2)
Programmable Devices	94	(2)
Physical Design	96	(11)
Floor Planning	96	(1)
Placement	97	(2)
Routing	99	(3)
Back-Annotation	102	(2)
References	104	(1)
Problems	105	(2)
PART II TEST FLOW	107	(80)
Role of Simulation in Testing	109	(22)
Introduction	109	(2)
Simulation of Large Designs	111	(1)
Test Benches	111	(1)
Cycle-Based Simulation	112	(1)
Logic Simulation	112	(1)
Approaches to Simulation	113	(2)
Compiled Simulation	113	(1)
Event-Driven Simulation	114	(1)
Timing Models	115	(3)
Static Timing Analysis	118	(1)
Mixed-Level Simulation	118	(1)
Fault Simulation	118	(8)
Parallel Fault Simulation	119	(3)
Deductive Simulation	122	(2)
Concurrent Fault Simulation	124	(2)
Fault Simulation Results	126	(5)
Fault Coverage	127	(1)
Fault Dictionary	128	(1)
References	129	(1)
Problems	130	(1)
Automatic Test Pattern Generation	131	(32)
Introduction	131	(1)
Terminology and Notation	132	(3)
Basic Operations	132	(1)
Logic and Set Operations	133	(1)
Fault List	134	(1)
The D-Algorithm	135	(5)
Case of an Internal Node	136	(3)
Case of a Primary Input	139	(1)
Case of a Primary Output	139	(1)
Alternative Strategies	140	(1)
Critical Path	140	(2)
Backtracking and Reconverging Fanout	142	(2)
PODEM	144	(1)
Other Algorithms	144	(4)
FAN Algorithm	147	(1)
SOCRATES	147	(1)
Testing Sequential Circuits	148	(15)
Functional Testing	149	(4)
Deterministic Test Pattern Generation	153	(7)
References	160	(1)
Problems	161	(2)
Current Testing	163	(24)
Introduction	163	(1)
Basic Concept	164	(3)
Fault-Free Current	167	(2)
Switching and Quiescent Currents	167	(1)
Switching Delays	168	(1)
Current-Sensing Techniques	169	(4)
Off-Chip Measurement	170	(2)
On-Chip Measurement	172	(1)
Fault Detection	173	(3)
Leakage Faults	174	(1)
Bridging Faults	175	(1)
Stuck-Open Faults	176	(1)
Delay Faults	176	(1)
Test Pattern Generation	176	(4)
Switch Level Model-Based	177	(2)
Leakage Fault Model-Based	179	(1)
Impact of Deep-Submicron Technology	180	(7)
References	182	(2)
Problems	184	(3)
PART III DESIGN FOR TESTABILITY	187	(108)
Ad Hoc Techniques	189	(26)
Introduction	189	(1)
Case for DFT	190	(2)
Test Generation and Application	190	(1)
Characteristics of Present VLSI	190	(2)
Testability Analysis	192	(4)
Initialization and Test Points	196	(3)
Initialization	197	(1)
Observation Points	197	(1)
Control Points	198	(1)
Partitioning for Testability	199	(7)
Easily Testable Circuits	206	(9)
C-Testability	207	(3)
Scalable Testing	210	(1)
References	211	(2)
Problems	213	(2)
Scan-Path Design	215	(26)
Introduction	215	(2)
Scan-Path Design	217	(1)
Test Pattern Generation	218	(1)
Test Pattern Application	219	(1)
Testing the Flip-Flops	219	(1)
Testing the Combinational Part of the Circuit	219	(1)
Example for Scan-Path Testing	220	(2)
Storage Devices	222	(2)
Two-Port Flip-Flop	222	(1)
Clocked Latch	223	(1)
Scan Architectures	224	(2)
Level-Sensitive Scan Design	224	(2)
Scan-Set Architecture	226	(1)
Multiple Scan Chains	226	(1)
Cost of Scan-Path Design	227	(2)
Extra Area and Pins	229	(1)
Performance	229	(1)
Test Application Time	229	(1)
Heat Dissipation	229	(1)
Partial Scan Testing	229	(4)
Definitions	231	(1)
Selecting Scan Flip-Flops	231	(2)
Test Application	233	(1)
Ordering Scan Chain Flip-Flops	233	(8)
Optimizing for Test Application	233	(2)
Optimizing Interconnect Wiring	235	(2)
References	237	(1)
Problems	238	(3)
Boundary-Scan Testing	241	(20)
Introduction	241	(1)
Traditional Board Testing	242	(1)
Boundary-Scan Architecture	243	(2)
Test Access Port	245	(1)
Registers	246	(4)
Boundary-Scan Cell	247	(1)
Bypass Register	248	(1)
Boundary-Scan Register	248	(1)
Instruction Register	248	(1)
Device Identification Register	249	(1)
TAP Controller	250	(4)
Controller's States	251	(1)
Instruction Set	251	(3)
Modes of Operations	254	(3)
Normal Operation	254	(1)
Test Mode Operation	254	(2)
Testing the Boundary-Scan Registers	256	(1)
Boundary-Scan Languages	257	(1)
Cost of Boundary-Scan Design	257	(1)
To Explore Further	258	(3)
References	258	(1)
Problems	259	(2)
Built-in Self-Test	261	(34)
Introduction	261	(1)
Pseudorandom test Pattern Generation	262	(9)
Linear Feedback Shift Register	262	(2)
LFSR Configurations	264	(2)
Mathematical Foundation of LFSR	266	(5)
Response Compaction	271	(10)
Parity Testing	272	(1)
One Counting	272	(1)
Transition Counting	273	(1)
Signature Analysis	274	(5)
Space Compaction	279	(2)
Random Pattern-Resistant Faults	281	(2)
BIST Architectures	283	(12)
Built-in Self-Testing	283	(1)
Autonomous Test	284	(1)
Circular BIST	284	(1)
BILBO	285	(2)
Random Test Socket	287	(1)
STUMPS	288	(2)
References	290	(1)
Problems	291	(4)
PART IV SPECIAL STRUCTURES	295	(56)
Memory Testing	297	(22)
Motivation	297	(1)
Memory Models	298	(3)
Functional Model	298	(1)
Memory Cell	299	(1)
RAM Organization	300	(1)
Defects and Fault Models	301	(4)
Defects	301	(1)
Array Fault Models	301	(4)
Surrounding Logic	305	(1)
Types of Memory Testing	305	(3)
Specification Testing	306	(1)
Characterization Testing	306	(1)
Functional Testing	306	(2)
Current Testing	308	(1)
Functional Testing Schemes	308	(4)
MSCAN	308	(1)
GALPAT Algorithm	308	(2)
Algorithmic Test Sequence	310	(1)
Marching Pattern Sequences	310	(1)
Checkerboard Test	311	(1)
Memory BIST	312	(2)
Memory Diagnosis and Repairs	314	(5)
References	315	(1)
Problems	316	(3)
Testing FPGAs and Microprocessors	319	(32)
Introduction	319	(1)
Field-Programmable Gate Arrays	320	(6)
Architecture	320	(4)
Programmability	324	(2)
Testability of FPGAs	326	(1)
Defects and Faults	326	(1)
Approaches to Testing FPGAs	326	(1)
Testing RAM-Based FPGAs	327	(6)
Functional Testing	327	(3)
IDDQ Testing	330	(1)
BIST	330	(2)
Diagnosis Testing	332	(1)
Microprocessors	333	(3)
Microprocessor Models	334	(2)
Microprocessor Validation	336	(1)
Testing Microprocessors	336	(4)
Instruction Set Verification	338	(1)
Testing the Datapath	339	(1)
DFT Features in Modern Microprocessors	340	(11)
Testing Sun Microsystems Processors	341	(1)
Testing Digital's Alpha 21164	341	(2)
Testing the Intel Pentium Pro	343	(1)
Testing AMD's K6	344	(1)
Testing IBM S/390	345	(1)
Testing Hewlett-Packard's PA 8500	346	(1)
References	346	(4)
Problems	350	(1)
PART V ADVANCED TOPICS	351	(50)
Synthesis for Testability	353	(24)
Introduction	353	(1)
Testability Concerns	354	(1)
Synthesis Revisited	354	(1)
High-Level Synthesis	355	(8)
Model Compilation	357	(1)
Transformations	358	(1)
Scheduling	359	(1)
Allocation and Binding	360	(3)
Test Synthesis Methodologies	363	(14)
Partitioning	364	(1)
Controllability and Observability	365	(1)
Feedback Loops	366	(2)
Scan Path	368	(2)
BIST Insertion	370	(3)
References	373	(2)
Problems	375	(2)
Testing SOCs	377	(24)
Introduction	377	(1)
Classification of Cores	378	(2)
Design and Test Flow	380	(2)
Core Test Requirements	382	(1)
Conceptional Test Architecture	383	(4)
Source and Sink of Test data	384	(1)
Test Access Mechanism	385	(1)
Core Test Wrapper	386	(1)
Testing Strategies	387	(9)
Direct Access Test Scheme	387	(1)
Use of Boundary-Scan	388	(4)
Use of Scan Path	392	(4)
To Explore Further	396	(5)
Virtual Socket Interface Alliance	396	(1)
IEEE P 1500 Standard	397	(1)
References	398	(1)
Problems	399	(2)
Appendix A---Bibliography	401	(6)
Appendix B---Terms and Acronyms	407	(4)
Index	411