Principles of VLSI RTL Design

Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written.#xA0; #xA0;Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.

Introduction to VLSI RTL Designs	p. 1
A Brief Background	p. 1
Hardware Description Languages (HDL)	p. 2
RTL Designs	p. 4
Design Goals and Constraints	p. 5
RTL Based Chip Design Flow	p. 6
Design Challenges	p. 7
Simulation Friendly RTL	p. 8
Timing-Analysis Friendly RTL	p. 9
Clock-Domain-Crossing (CDC) Friendly RTL	p. 13
Power Friendly RTL	p. 14
DFT Friendly RTL	p. 16
Timing-Exceptions Friendly RTL	p. 17
Congestion Conscious RTL	p. 19
Summary	p. 20
Ensuring RTL Intent	p. 21
Need for Unambiguous Simulation	p. 21
Simulation Race	p. 22
Read-Write Race	p. 22
Write-Write Race	p. 24
Always-Initial Race	p. 26
Race Due to Inter-leaving of Assign with Procedural Block	p. 27
Avoiding Simulation Race	p. 28
Feedthroughs	p. 28
Feedthroughs Because of Races	p. 29
Feedthroughs Without Simulation Race	p. 30
VHDL Feedthroughs	p. 30
Simulation-Synthesis Mismatch	p. 32
Latch Inference	p. 34
Synchronous Reset	p. 36
Limitations of Simulation	p. 40
Timing Analysis	p. 43
ScopeofSTA	p. 43
Simulation Limitations in the Context of Timing	p. 44
Exhaustiveness of STA	p. 45
Timing Parameters for Digital Logic	p. 45
Delay Parameters	p. 45
Slew Parameters for Digital Logic	p. 47
Delay and Slew Measurement	p. 48
Factors Affecting Delay and Slew	p. 49
Discrete Factors	p. 49
Continuous Factors	p. 53
Sequential Arcs	p. 58
Pulse Width	p. 58
Setup	p. 59
Hold	p. 59
Recovery	p. 60
Removal	p. 60
Understanding Setup and Hold	p. 60
Understanding Setup	p. 61
Understanding Hold	p. 62
Negative Timing Check	p. 62
Basic Analysis	p. 63
Uncertainty	p. 66
STA Contrasted with Simulation	p. 67
Setup Violation in STA, No Violation in Simulation	p. 68
Setup Violation in STA, Hold Violation in Simulation	p. 68
Hold Violation in STA, Setup Violation in Simulation	p. 68
Accurate Timing Simulation	p. 69
Limitations of Static Timing Analysis	p. 70
SSTA	p. 71
Conclusion	p. 71
Clock Domain Crossing (CDC)	p. 73
Clock Domain	p. 73
Metastability Due to CDC	p. 74
Understanding Metastability	p. 74
Problems Due to Metastability	p. 75
Synchronizer	p. 76
Double Flop Synchronizer	p. 76
Mean Time Between Failures (MTBF)	p. 77
Meta Hardened Flops	p. 78
Bus Synchronization	p. 78
Challenge with Bus Synchronization	p. 78
Grey Encoding	p. 79
Enable Synchronization Method	p. 79
Cost of Enable Synchronization	p. 80
Data Loss	p. 81
Slow to Fast Crossing	p. 81
Fast to Slow Crossing	p. 82
Preventing Data Loss Through FIFO	p. 83
FIFO Basics	p. 83
Full and Empty Generation	p. 84
FIFO Limitations	p. 85
Other Reliability Concerns	p. 85
Catching CDC	p. 87
Using STA	p. 87
Using Simulation	p. 87
Using Rule Checkers	p. 88
Domain Revisited	p. 88
Power	p. 91
Importance of Low Power	p. 91
Increasing Device Density	p. 91
Increasing Speed	p. 91
Battery Life	p. 92
Green Concerns	p. 92
User Experience	p. 92
Causes of Power Dissipation	p. 92
Factors Affecting Power	p. 95
Switching Activity	p. 95
Capadtive Load	p. 95
Supply Voltage	p. 95
Transition Rate	p. 96
Device Characteristics	p. 96
Device State	p. 96
Switching Activity	p. 96
Shifter Instead of Multipliers	p. 97
Operand Isolation	p. 97
Avoid Comparison	p. 98
Clock Gating	p. 99
Supply Voltage	p. 106
Simulation Limitation	p. 107
Implication on Synthesis	p. 108
Implication on Backend	p. 108
Selective Shut Down	p. 109
Need for Isolation	p. 110
Generation of Power-Enable	p. 11l
Power Sequencing	p. 112
Load Capacitance	p. 112
Input Transition	p. 112
Device Characteristics	p. 113
Power Estimation	p. 113
Internal Power Estimation	p. 116
Switching Power Estimation	p. 117
Leakage Power Estimation	p. 117
Power Estimation at Non-gate Level	p. 117
Probabilistic Estimation	p. 118
Spatial Correlation	p. 119
Temporal Correlation	p. 121
Simulation Plus Probabilistic	p. 121
CPF/UPF	p. 123
Design for Test (DFT)	p. 125
Introduction	p. 125
Manufacturing Defect - Vis-a-Vis - Design Defect	p. 125
Stuck-At Fault Models	p. 126
Cost Considerations	p. 126
Controllability and Observability	p. 126
Controllability and Observability Conflict	p. 127
Scan Chains	p. 128
Need for Simultaneous Control	p. 128
Complexity Due to Signal Relationship	p. 129
Need for Many Control and Observe Points	p. 130
Using Scan Chain for Controllability and Observability	p. 130
Mechanics of Scan Chain	p. 131
Scan Flop	p. 131
Replacing Flops with Scan Versions	p. 132
Timing Impact of Scan Flops	p. 132
Area Impact of Scan Flops	p. 133
Stitching the Chain	p. 133
Shift and Capture	p. 133
ShiftIn	p. 134
Capture	p. 134
ShiftOut	p. 135
Overlapping ShiftIn and ShiftOut	p. 135
Chain Length	p. 136
Pseudo Random Flop Outputs	p. 136
Tristate Controls	p. 137
Uncontrollable Flops	p. 137
Shadow Registers	p. 138
Observability	p. 138
Scan Wrap	p. 139
Memory Testing	p. 140
Latch Based Designs	p. 140
Combinational Loops	p. 142
Power Impact	p. 143
Transitions Fault Model	p. 144
Conclusion	p. 144
Timing Exceptions	p. 147
False Paths	p. 147
False Paths Due to Specific Protocol	p. 148
False Paths Due to Paths Being Unsensitizable	p. 148
False Paths Due to CDC	p. 150
False Paths Due to Multi Mode	p. 151
False Paths Due to Pin Muxing	p. 152
False Paths Due to Exclusive Clocks	p. 154
False Paths Due to Asynchronous Control Signals	p. 155
False Paths Due to Quasi Static Signals	p. 156
set_false_path-vs-set_clock_groups	p. 156
Disable Timing	p. 157
Multi Cycle Paths	p. 158
Slow to Fast Clock Transfer of Data	p. 158
Fast to Slow Clock Transfer of Data	p. 161
Protocol Based Data Transfer	p. 163
Multicycle Paths for False Paths	p. 164
Multicycle Paths for Deep Logic	p. 164
Conclusion	p. 165
Congestion	p. 167
Impact of Congestion	p. 167
Physical Design Basics	p. 168
RTL Characteristics	p. 168
High Utilization	p. 169
Large Macros	p. 170
Interaction with Many Blocks	p. 171
Too Many Critical Paths	p. 172
Feedthrough	p. 173
Conclusion	p. 174
Interleaving of Processes	p. 175
Index	p. 177
Table of Contents provided by Ingram. All Rights Reserved.

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