Rapid Prototyping of Digital Systems

by Hamblen, James O.; Furman, Michael D.

• ISBN13: 9780792374398
• ISBN10: 0792374398
• Edition: 2nd
• Format: Paperback
• Copyright: 2001-09-01
• Publisher: Kluwer Academic Pub

Summary

Rapid Prototyping of Digital Systems, Second Edition provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic. Design engineers working in industry will also want to consider this book for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, especially if they have not had previous experience with the new and rapidly evolving technology. Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy-to-use input and output functions were developed for this book to help the reader get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis. The second edition of the text now includes Altera's 10.1 student edition software which adds support for Windows 2000 and designs that are three times larger using the new 70,000 gate UP 1X board. All designs in the book's CD-Rom have been updated to work with the original UP 1 board or the newer UP 1X board using the new Altera student version software. A coupon is included with the text for purchase of the new UP 1X board. The additional logic and memory in the UP 1X's FLEX 10K70 is useful on larger design projects such as computers and video games. In addition to the new software, the second edition includes an update chapter on programmable logic, new robot sensors and projects, optional Verilog examples, and a meta assembler which can be used to develop assemble language programs for the computer designs in Chapters 8 and 13.

Table of Contents

Tutorial I: The 15 Minute Design	p. 2
Design Entry using the Graphic Editor	p. 6
Compiling the Design	p. 9
Simulation of the Design	p. 10
Downloading Your Design to the UP 1 or UP 1X Board	p. 12
The 10 Minute VHDL Entry Tutorial	p. 14
Compiling the VHDL Design	p. 17
The 10 Minute Verilog Entry Tutorial	p. 17
Compiling the Verilog Design	p. 21
Timing Analysis	p. 22
The Floorplan Editor	p. 23
Symbols and Hierarchy	p. 24
Functional Simulation	p. 24
For additional information	p. 25
Laboratory Exercises	p. 25
The Altera UP 1 and UP 1X CPLD Boards	p. 30
Programming Jumpers	p. 31
MAX 7000 Device and UP 1 I/O Features	p. 31
MAX and FLEX Seven-segment LED Displays	p. 31
FLEX 10K Device and UP 1 I/O Features	p. 34
Obtaining a UP 1 or UP 1X Board and Power Supply	p. 36
Programmable Logic Technology	p. 38
CPLDs and FPGAs	p. 41
Altera MAX 7000S Architecture--A Product Term CPLD Device	p. 42
Altera FLEX 10K Architecture--A Look-Up Table CPLD Device	p. 43
Xilinx 4000 Architecture--A Look-Up Table FPGA Device	p. 47
Computer Aided Design Tools for Programmable Logic	p. 49
Next Generation FPLD CAD tools	p. 50
Applications of FPLDs	p. 50
Features of New Generation FPLDs	p. 50
For additional information	p. 51
Laboratory Exercises	p. 52
Tutorial II: Sequential Design and Hierarchy	p. 54
Install the Tutorial Files and UP1core Library	p. 54
Open the tutor2 Schematic	p. 54
Browse the Hierarchy	p. 56
Using Buses in a Schematic	p. 57
Testing the Pushbutton Counter and Displays	p. 58
Testing the Initial Design on the UP 1 Board	p. 59
Fixing the Switch Contact Bounce Problem	p. 60
Testing the Modified Design on the UP 1 Board	p. 61
Laboratory Exercises	p. 61
UP1core Library Functions	p. 66
UP1core DEC_7SEG: Hex to Seven-segment Decoder	p. 67
UP1core Debounce: Pushbutton Debounce	p. 68
UP1core OnePulse: Pushbutton Single Pulse	p. 69
UP1core Clk_Div: Clock Divider	p. 70
UP1core VGA_Sync: VGA Video Sync Generation	p. 71
UP1core CHAR_ROM: Character Generation ROM	p. 73
UP1core Keyboard: Read Keyboard Scan Code	p. 74
UP1core Mouse: Mouse Cursor	p. 75
Using VHDL for Synthesis of Digital Hardware	p. 78
VHDL Data Types	p. 78
VHDL Operators	p. 79
VHDL Based Synthesis of Digital Hardware	p. 80
VHDL Synthesis Models of Gate Networks	p. 80
VHDL Synthesis Model of a Seven-segment LED Decoder	p. 81
VHDL Synthesis Model of a Multiplexer	p. 83
VHDL Synthesis Model of Tri-State Output	p. 84
VHDL Synthesis Models of Flip-flops and Registers	p. 84
Accidental Synthesis of Inferred Latches	p. 86
VHDL Synthesis Model of a Counter	p. 86
VHDL Synthesis Model of a State Machine	p. 87
VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter	p. 89
VHDL Synthesis of Multiply and Divide Hardware	p. 90
VHDL Synthesis Models for Memory	p. 91
Hierarchy in VHDL Synthesis Models	p. 94
Using a Testbench for Verification	p. 96
For additional information	p. 97
Laboratory Exercises	p. 97
State Machine Design: The Electric Train Controller	p. 102
The Train Control Problem	p. 102
Track Power (T1, T2, T3, and T4)	p. 104
Track Direction (DA1-DA0, and DB1-DB0)	p. 104
Switch Direction (SW1, SW2, and SW3)	p. 105
Train Sensor Input Signals (S1, S2, S3, S4, and S5)	p. 105
An Example Controller Design	p. 106
VHDL Based Example Controller Design	p. 110
Simulation Vector file for State Machine Simulation	p. 112
Running the Train Control Simulation	p. 115
Running the Video Train System (After Successful Simulation)	p. 116
Laboratory Exercises	p. 117
A Simple Computer Design: The [mu]P 1	p. 122
Computer Programs and Instructions	p. 123
The Processor Fetch, Decode and Execute Cycle	p. 124
VHDL Model of the [mu]P 1	p. 131
Simulation of the [mu]P1 Computer	p. 134
Laboratory Exercises	p. 135
VGA Video Display Generation	p. 140
Video Display Technology	p. 140
Video Refresh	p. 140
Using a CPLD for VGA Video Signal Generation	p. 143
A VHDL Sync Generation Example: UP1core VGA_SYNC	p. 144
Final Output Register for Video Signals	p. 146
Required Pin Assignments for Video Output	p. 146
Video Examples	p. 147
A Character Based Video Design	p. 147
Character Selection and Fonts	p. 148
VHDL Character Display Design Examples	p. 151
A Graphics Memory Design Example	p. 153
Video Data Compression	p. 154
Video Color Mixing using Dithering	p. 155
VHDL Graphics Display Design Example	p. 155
Laboratory Exercises	p. 157
Communications: Interfacing to the PS/2 Keyboard	p. 160
PS/2 Port Connections	p. 160
Keyboard Scan Codes	p. 161
Make and Break Codes	p. 161
The PS/2 Serial Data Transmission Protocol	p. 161
Scan Code Set 2 for the PS/2 Keyboard	p. 164
The Keyboard UP1core	p. 166
A Design Example Using the Keyboard UP1core	p. 169
For Additional Information	p. 170
Laboratory Exercises	p. 170
Communications: Interfacing to the PS/2 Mouse	p. 172
The Mouse UP1core	p. 174
Mouse Initialization	p. 174
Mouse Data Packet Processing	p. 175
An Example Design Using the Mouse UP1core	p. 176
For Additional Information	p. 176
Laboratory Exercises	p. 176
Robotics: The UP1-bot	p. 178
The UP1-bot Design	p. 178
UP1-bot Servo Drive Motors	p. 178
Modifying the Servos to make Drive Motors	p. 179
VHDL Servo Driver Code for the UP1-bot	p. 180
Sensors for the UP1-bot	p. 182
Assembly of the UP1-bot Body	p. 190
UP1-bot FLEX Expansion B Header Pins	p. 197
An Alternative UP 1 Robot Project Based on an R/C Car	p. 198
For Additional Information	p. 203
Laboratory Exercises	p. 204
A RISC Design: Synthesis of the MIPS Processor Core	p. 210
The MIPS Instruction Set and Processor	p. 210
Using VHDL to Synthesize the MIPS Processor Core	p. 213
The Top-Level Module	p. 214
The Control Unit	p. 217
The Instruction Fetch Stage	p. 219
The Decode Stage	p. 222
The Execute Stage	p. 224
The Data Memory Stage	p. 226
Simulation of the MIPS Design	p. 227
MIPS Hardware Implementation on the UP 1 or UP 1X Board	p. 228
For Additional Information	p. 229
Laboratory Exercises	p. 230
Generation of Pseudo Random Binary Sequences	p. 235
MAX+PLUS II Design and Data File Extensions	p. 237
UP 1 and UP 1X Pin Assignments	p. 239
The Wintim Meta Assembler	p. 243
An Introduction to Verilog for VHDL users	p. 252
Glossary	p. 259
Index	p. 267
About the Accompanying CD-ROM	p. 270
Table of Contents provided by Syndetics. All Rights Reserved.