Rapid Prototyping of Digital Systems : Quartus(r) II Edition

by Hamblen, James O.; Hall, Tyson S.; Furman, Michael D.

• ISBN13: 9780387277288
• ISBN10: 0387277285
• Edition: 3rd
• Format: Paperback
• Copyright: 2005-10-01
• Publisher: Springer Verlag

Summary

Rapid Prototyping of Digital Systems: Quartus II Edition provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses using FPGAs and CAD tools for simulation and hardware implementation. The more advanced topics and exercises also make this text useful for upper level courses in digital logic, programmable logic, and embedded systems. This new version of the widely used Rapid Prototyping of Digital Systems, Second Edition, now uses Altera's new Quartus II CAD tool and includes laboratory projects for Altera's UP 2 and the new UP 3 FPGA board. Student laboratory projects provided on the book's CD-ROM include video graphics and text, mouse and keyboard input, and three computer designs.Rapid Prototyping of Digital Systems: Quartus II Edition includes four tutorials on the Altera Quartus II and NIOS II tool environment, an overview of programmable logic, and IP cores with several easy-to-use input and output functions. These features were developed to help students get started quickly. Early design examples use schematic capture and IP cores developed for the Altera UP FPGA boards. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis. New to this edition is an overview of System-on-a-Programmable Chip (SOPC) technology and SOPC design examples for the UP3 using Altera's new NIOS II Processor hardware and C software development tools. A full set of Altera's FPGA CAD tools is included on the book's CD-ROM.

Table of Contents

Tutorial I: The 15 Minute Design	2	(36)
Design Entry using the Graphic Editor	7	(6)
Compiling the Design	13	(1)
Simulation of the Design	14	(1)
Downloading Your Design to the UP 3 Board	15	(3)
Downloading Your Design to the UP 2 Board	18	(2)
The 10 Minute VHDL Entry Tutorial	20	(3)
Compiling the VHDL Design	23	(1)
The 10 Minute Verilog Entry Tutorial	24	(2)
Compiling the Verilog Design	26	(1)
Timing Analysis	27	(1)
The Floorplan Editor	28	(2)
Symbols and Hierarchy	30	(1)
Functional Simulation	30	(1)
Laboratory Exercises	31	(5)
The Altera UP 3 Board	36	(8)
The UP 3 Cyclone FPGA Features	37	(1)
The UP 3 Board's Memory Features	38	(1)
The UP 3 Board's I/O Features	38	(3)
Obtaining a UP 3 Board and Cables	41	(3)
Programmable Logic Technology	44	(18)
CPLDs and FPGAs	47	(1)
Altera MAX 7000S Architecture -- A Product Term CPLD Device	48	(2)
Altera Cyclone Architecture -- A Look-Up Table FPGA Device	50	(3)
Xilinx 4000 Architecture -- A Look-Up Table FPGA Device	53	(2)
Computer Aided Design Tools for Programmable Logic	55	(1)
Next Generation FPGA CAD tools	56	(1)
Applications of FPGAs	57	(1)
Features of New Generation FPGAs	57	(1)
For additional information	58	(1)
Laboratory Exercises	58	(4)
Tutorial II: Sequential Design and Hierarchy	62	(12)
Install the Tutorial Files and UP3core Library	62	(1)
Open the tutor 2 Schematic	63	(1)
Browse the Hierarchy	63	(2)
Using Buses in a Schematic	65	(1)
Testing the Pushbutton Counter and Displays	66	(1)
Testing the Initial Design on the Board	67	(1)
Fixing the Switch Contact Bounce Problem	68	(1)
Testing the Modified Design on the UP 3 Board	69	(1)
Laboratory Exercises	69	(5)
UP3core Library Functions	74	(14)
UP3core LCD_Display: LCD Panel Character Display	76	(1)
UP3core Debounce: Pushbutton Debounce	77	(1)
UP3core OnePulse: Pushbutton Single Pulse	78	(1)
UP3core Clk_Div: Clock Divider	79	(1)
UP3core VGA_Sync: VGA Video Sync Generation	80	(2)
UP3core Char_ROM: Character Generation ROM	82	(1)
UP3core Keyboard: Read Keyboard Scan Code	83	(1)
UP3core Mouse: Mouse Cursor	84	(1)
For additional information	85	(3)
Using VHDL for Synthesis of Digital Hardware	88	(24)
VHDL Data Types	88	(1)
VHDL Operators	89	(1)
VHDL Based Synthesis of Digital Hardware	90	(1)
VHDL Synthesis Models of Gate Networks	90	(1)
VHDL Synthesis Model of a Seven-segment LED Decoder	91	(2)
VHDL Synthesis Model of a Multiplexer	93	(1)
VHDL Synthesis Model of Tri-State Output	94	(1)
VHDL Synthesis Models of Flip-flops and Registers	94	(2)
Accidental Synthesis of Inferred Latches	96	(1)
VHDL Synthesis Model of a Counter	96	(1)
VHDL Synthesis Model of a State Machine	97	(2)
VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter	99	(1)
VHDL Synthesis of Multiply and Divide Hardware	100	(1)
VHDL Synthesis Models for Memory	101	(4)
Hierarchy in VHDL Synthesis Models	105	(2)
Using a Testbench for Verification	107	(1)
For additional information	108	(1)
Laboratory Exercises	108	(4)
Using Verilog for Synthesis of Digital Hardware	112	(18)
Verilog Data Types	112	(1)
Verilog Based Synthesis of Digital Hardware	112	(1)
Verilog Operators	113	(1)
Verilog Synthesis Models of Gate Networks	114	(1)
Verilog Synthesis Model of a Seven-segment LED Decoder	114	(1)
Verilog Synthesis Model of a Multiplexer	115	(1)
Verilog Synthesis Model of Tri-State Output	116	(1)
Verilog Synthesis Models of Flip-flops and Registers	117	(1)
Accidental Synthesis of Inferred Latches	118	(1)
Verilog Synthesis Model of a Counter	118	(1)
Verilog Synthesis Model of a State Machine	119	(1)
Verilog Synthesis Model of an ALU with an Adder/Subtractor and a Shifter	120	(1)
Verilog Synthesis of Multiply and Divide Hardware	121	(1)
Verilog Synthesis Models for Memory	122	(3)
Hierarchy in Verilog Synthesis Models	125	(1)
For additional information	126	(1)
Laboratory Exercises	126	(4)
State Machine Design: The Electric Train Controller	130	(18)
The Train Control Problem	130	(2)
Track Power (T1, T2, T3, and T4)	132	(1)
Track Direction (DA1-DA0, and DB1-DB0)	132	(1)
Switch Direction (SW1, SW2, and SW3)	133	(1)
Train Sensor Input Signals (S1, S2, S3, S4, and S5)	133	(1)
An Example Controller Design	134	(4)
VHDL Based Example Controller Design	138	(2)
Simulation Vector file for State Machine Simulation	140	(2)
Running the Train Control Simulation	142	(1)
Running the Video Train System (After Successful Simulation)	142	(2)
Laboratory Exercises	144	(4)
A Simple Computer Design: The μP 3	148	(20)
Computer Programs and Instructions	149	(1)
The Processor Fetch, Decode and Execute Cycle	150	(7)
VHDL Model of the μP 3	157	(4)
Simulation of the uP3 Computer	161	(1)
Laboratory Exercises	162	(6)
VGA Video Display Generation	168	(20)
Video Display Technology	168	(1)
Video Refresh	168	(3)
Using an FPGA for VGA Video Signal Generation	171	(1)
A VHDL Sync Generation Example: UP3core VGA_SYNC	172	(2)
Final Output Register for Video Signals	174	(1)
Required Pin Assignments for Video Output	174	(1)
Video Examples	175	(1)
A Character Based Video Design	176	(1)
Character Selection and Fonts	176	(3)
VHDL Character Display Design Examples	179	(2)
A Graphics Memory Design Example	181	(1)
Video Data Compression	182	(1)
Video Color Mixing using Dithering	183	(1)
VHDL Graphics Display Design Example	183	(2)
Higher Video Resolution and Faster Refresh Rates	185	(1)
Laboratory Exercises	185	(3)
Interfacing to the PS/2 Keyboard and Mouse	188	(18)
PS/2 Port Connections	188	(1)
Keyboard Scan Codes	189	(1)
Make and Break Codes	189	(1)
The PS/2 Serial Data Transmission Protocol	190	(2)
Scan Code Set 2 for the PS/2 Keyboard	192	(2)
The Keyboard UP3core	194	(3)
A Design Example Using the Keyboard UP3core	197	(1)
Interfacing to the PS/2 Mouse	198	(2)
The Mouse UP3core	200	(1)
Mouse Initialization	200	(1)
Mouse Data Packet Processing	201	(1)
An Example Design Using the Mouse UP3core	202	(1)
For Additional Information	202	(1)
Laboratory Exercises	203	(3)
Legacy Digital I/O Interfacing Standards	206	(10)
Parallel I/O Interface	206	(1)
RS-232C Serial I/O Interface	207	(2)
SPI Bus Interface	209	(2)
I2C Bus Interface	211	(2)
For Additional Information	213	(1)
Laboratory Exercises	213	(3)
UP 3 Robotics Projects	216	(40)
The UP3-bot Design	216	(1)
UP3-bot Servo Drive Motors	216	(1)
Modifying the Servos to make Drive Motors	217	(1)
VHDL Servo Driver Code for the UP3-bot	218	(2)
Low-cost Sensors for a UP 3 Robot Project	220	(13)
Assembly of the UP3-bot Body	233	(7)
I/O Connections to the UP 3's Expansion Headers	240	(2)
Robot Projects Based on R/C Toys, Models, and Robot Kits	242	(6)
For Additional Information	248	(2)
Laboratory Exercises	250	(6)
A RISC Design: Synthesis of the MIPS Processor Core	256	(26)
The MIPS Instruction Set and Processor	256	(3)
Using VHDL to Synthesize the MIPS Processor Core	259	(1)
The Top-Level Module	260	(3)
The Control Unit	263	(2)
The Instruction Fetch Stage	265	(3)
The Decode Stage	268	(2)
The Execute Stage	270	(2)
The Data Memory Stage	272	(1)
Simulation of the MIPS Design	273	(1)
MIPS Hardware Implementation on the UP 3 Board	274	(1)
For Additional Information	275	(1)
Laboratory Exercises	276	(6)
Introducing System-on-a-Programmable-Chip	282	(12)
Processor Cores	282	(1)
SOPC Design Flow	283	(2)
Initializing Memory	285	(2)
SOPC Design versus Traditional Design Modalities	287	(1)
An Example SOPC Design	288	(1)
Hardware/Software Design Alternatives	289	(1)
For additional information	289	(1)
Laboratory Exercises	290	(4)
Tutorial III: Nios II Processor Software Development	294	(30)
Install the UP 3 board files	294	(1)
Starting a Nios II Software Project	294	(2)
The Nios II IDE Software	296	(1)
Generating the Nios II System Library	297	(1)
Software Design with Nios II Peripherals	298	(3)
Starting Software Design -- main()	301	(1)
Downloading the Nios II Hardware and Software Projects	302	(1)
Executing the Software	303	(1)
Starting Software Design for a Peripheral Test Program	303	(3)
Handling Interrupts	306	(1)
Accessing Parallel I/O Peripherals	307	(1)
Communicating with the LCD Display	308	(3)
Testing SRAM	311	(1)
Testing Flash Memory	312	(1)
Testing SDRAM	313	(5)
Downloading the Nios II Hardware and Software Projects	318	(1)
Executing the Software	319	(1)
For additional information	320	(1)
Laboratory Exercises	320	(4)
Tutorial IV: Nios II Processor Hardware Design	324	(21)
Install the UP 3 board files	324	(1)
Creating a New Project	324	(1)
Starting SOPC Builder	325	(2)
Adding a Nios II Processor	327	(2)
Adding UART Peripherals	329	(1)
Adding an Interval Timer Peripheral	330	(1)
Adding Parallel I/O Components	331	(1)
Adding a SDRAM Memory Controller	332	(1)
Adding an External Bus	333	(1)
Adding Components to the External Bus	334	(1)
Global Processor Settings	335	(2)
Finalizing the Nios II Processor	337	(1)
Add the Processor Symbol to the Top-Level Schematic	337	(1)
Create a Phase-Locked Loop Component	338	(1)
Add the UP 3 External Bus Multiplexer Component	339	(1)
Complete the Top-Level Schematic	339	(1)
Design Compilation	339	(2)
Testing the Nios II Project	341	(1)
For additional information	341	(1)
Laboratory Exercises	341	(4)
Appendix A: Generation of Pseudo Random Binary Sequences	345	(2)
Appendix B: Quartus II Design and Data File Extensions	347	(2)
Appendix C: UP 3 Pin Assignments	349	(6)
Appendix D: ASCII Character Code	355	(2)
Appendix E: Programming the UP 3's Flash Memory	357	(2)
Glossary	359	(8)
Index	367	(4)
About the Accompanying CD-ROM	371