Rapid Prototyping of Digital Systems

by Hamblen, James O.; Furman, Michael D.

• ISBN13: 9780792386049
• ISBN10: 0792386043
• Edition: CD
• Format: Paperback
• Copyright: 1999-08-01
• Publisher: Kluwer Academic Pub

Table of Contents

Tutorial I: The 15 Minute Design	2	(28)
Design Entry using the Graphic Editor	6	(3)
Compiling the Design	9	(1)
Simulation of the Design	10	(2)
Downloading Your Design to the UP 1 Board	12	(2)
The 10 Minute VHDL Entry Tutorial	14	(3)
Compiling the VHDL Design	17	(1)
The 10 Minute Verilog Entry Tutorial	17	(4)
Compiling the Verilog Design	21	(1)
Timing Analysis	22	(1)
The Floorplan Editor	23	(1)
Symbols and Hierarchy	24	(1)
Functional Simulation	24	(1)
For additional information	24	(1)
Laboratory Exercises	25	(5)
The Altera UP 1 CPLD Board	30	(8)
Programming Jumpers	31	(1)
MAX 7000 Device and UP 1 I/O Features	31	(1)
MAX and FLEX Seven-segment LED Displays	31	(3)
FLEX 10K Device and UP 1 I/O Features	34	(2)
Obtaining a UP 1 Board and Power Supply	36	(2)
Programmable Logic Technology	38	(14)
CPLDs and FPGAs	40	(1)
Altera MAX 7000S Architecture -- A Product Term CPLD Device	41	(1)
Altera FLEX 10K Architecture -- A Look-Up Table CPLD Device	42	(4)
Xilinx 4000 Architecture -- A Look-Up Table FPGA Device	46	(2)
Computer Aided Design Tools for Programmable Logic	48	(1)
Applications of FPLDs	48	(1)
For Additional Information	49	(1)
Laboratory Exercises	49	(3)
Tutorial II: Sequential Design and Hierarchy	52	(12)
Install the Tutorial Files and UP1 core Library	52	(1)
Open the Tutor2 Schematic	52	(2)
Browse the Hierarchy	54	(1)
Using Buses in a Schematic	55	(1)
Testing the Pushbutton Counter and Displays	56	(1)
Testing the Initial Design on the UP 1 Board.	57	(1)
Fixing the Switch Contact Bounce Problem	58	(1)
Testing the Modified Design on the UP 1 Board.	59	(1)
Laboratory Exercises	59	(5)
UP1core Library Functions	64	(12)
UP1core DEC-7SEG: Hex to Seven-segment Decoder	65	(1)
UP1core Debounce: Pushbutton Debounce	66	(1)
UP1core OnePulse: Pushbutton Single Pulse	67	(1)
UP1core Clk_Div: Clock Divider	68	(1)
UP1core VGA_Sync: VGA Video Sync Generation	69	(2)
UP1core CHAR_ROM: Character Generation ROM	71	(1)
UP1core Keyboard: Read Keyboard Scan Code	72	(1)
UP1core Mouse: Mouse Cursor	73	(3)
Using VHDL for Synthesis of Digital Hardware	76	(24)
VHDL Data Types	76	(1)
VHDL Operators	77	(1)
VHDL Based Synthesis of Digital Hardware	78	(1)
VHDL Synthesis Models of Gate Networks	78	(1)
VHDL Synthesis Model of a Seven-segment LED Decoder	79	(2)
VHDL Synthesis Model of a Multiplexer	81	(1)
VHDL Synthesis Model of Tri-State Output	82	(1)
VHDL Synthesis Models of Flip-flops and Registers	82	(2)
Accidental Synthesis of Inferred Latches	84	(1)
VHDL Synthesis Model of a Counter	84	(1)
VHDL Synthesis Model of a State Machine	85	(2)
VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter	87	(1)
VHDL Synthesis of Multiply and Divide Hardware	88	(1)
VHDL Synthesis Models for Memory	89	(3)
Hierarchy in VHDL Synthesis Models	92	(2)
Using a Testbench for Verification	94	(1)
For Additional Information	95	(1)
Laboratory Exercises	95	(5)
State Machine Design: The Electric Train Controller	100	(20)
The Train Control Problem	100	(2)
Track Power (T1,T2,T3, and T4)	102	(1)
Track Direction (DA1-DA0, and DB1-DB0)	102	(1)
Switch Direction (SW1,SW2, and SW3)	103	(1)
Train Sensor Input Signals (S1,S2,S3,S4,and S5)	103	(1)
An Example Controller Design	104	(4)
VHDL Based Example Controller Design	108	(2)
Simulation Vector File for State Machine Simulation	110	(3)
Running the Train Control Simulation	113	(1)
Running the Video Train System (After Successful Simulation)	114	(1)
Laboratory Exercises	115	(5)
A Simple Computer Design: The μP 1	120	(14)
Computer Programs and Instructions	121	(1)
The Processor Fetch, Decode and Execute Cycle	122	(4)
VHDL Model of the μP 1	126	(3)
Simulation of the μP 1 Computer	129	(1)
Laboratory Exercises	130	(4)
VGA Video Display Generation	134	(20)
Video Display Technology	134	(1)
Video Refresh	134	(3)
Using a CPLD for VGA Video Signal Generation	137	(1)
A VHDL Sync Generation Example: UP1core VGA_SYNC	138	(2)
Final Output Register for Video Signals	140	(1)
Required Pin Assignments for Video Output	140	(1)
Video Examples	141	(1)
A Character Based Video Design	141	(1)
Character Selection and Fonts	142	(3)
VHDL Character Display Design Examples	145	(2)
A Graphics memory design example	147	(1)
Video Data Compression	148	(1)
Video Color Mixing using Dithering	149	(1)
VHDL Graphics Display Design Example	149	(2)
Laboratory Exercises	151	(3)
Communications: Interfacing to the PS/2 Keyboard	154	(12)
PS/2 Port Connections	154	(1)
Keyboard Scan Codes	155	(1)
Make and Break Codes	155	(1)
The PS/2 Serial Data Transmission Protocol	155	(3)
Scan Code Set 2 for the PS/2 Keyboard	158	(2)
The Keyboard UP1core	160	(3)
A design example using the Keyboard UP1core	163	(1)
For additional information	164	(1)
Laboratory Exercises	164	(2)
Communications: Interfacing to the PS/2 Mouse	166	(6)
The Mouse UP1core	168	(1)
Mouse Initialization	168	(1)
Mouse Data Packet Processing	169	(1)
An example design using the Mouse UP1core	170	(1)
For additional information	170	(1)
Laboratory Exercises	170	(2)
Robotics: The UP1-bot	172	(24)
The UP1-bot Design	172	(1)
UP1-bot Servo Drive Motors	172	(1)
Modifying the Servos to make Drive Motors	173	(1)
VHDL Servo Driver Code for the UP1-bot	174	(2)
Sensors for the UP1-bot	176	(5)
Assembly of the UP1-bot Body	181	(7)
UP1-bot FLEX Expansion B Header Pins	188	(1)
For Additional Information	189	(1)
Laboratory Exercises	190	(6)
A RISC Design: Synthesis of the MIPS Processor Core	196	(25)
The MIPS Instruction Set and Processor	196	(3)
Using VHDL to Synthesize the MIPS Processor Core	199	(1)
The Top Level Module	200	(3)
The Control Unit	203	(2)
The Instruction Fetch Stage	205	(3)
The Decode Stage	208	(2)
The Execute Stage	210	(2)
The Data Memory Stage	212	(1)
Simulation of the MIPS Design	213	(1)
MIPS Hardware Implementation on the UP 1 Board	214	(1)
For Additional Information	215	(1)
Laboratory Exercises	216	(5)
Appendix A: Generation of Pseudo Random Binary Sequences	221	(2)
Appendix B: MAX+PLUS II Design and Data File Extensions	223	(2)
Appendix C: UP 1 Pin Assignments	225	(3)
Glossary	228	(9)
Index	237	(3)
About the Accompanying CD-ROM	240