Reconfigurable Computing: Architectures, Tools and Applications : 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings

by Phaophak, Sirisuk; Morgan, Fearghal; El-Ghazawi, Tarek; Amano, Hideharu

• ISBN13: 9783642121326
• ISBN10: 3642121322
• Format: Paperback
• Copyright: 2010-04-21
• Publisher: Springer Verlag

Summary

This book constitutes the proceedings of the 6th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2010, held in Bangkok Thailand, in March 2010. The 42 papers presented, consisting of 26 full and 16 short papers, were carefully reviewed and selected from numerous submissions. The topics covered are practical applications of the RC technology, RC architectures, TC design methodologies and tools, and RC education.

Table of Contents

Keynotes (Abstracts)
High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors	p. 1
Process Variability and Degradation: New Frontier for Reconfigurable	p. 2
Towards Analytical Methods of FPGA Architecture Investigation	p. 3
Architectures 1
Generic Systolic Array for Run-Time Scalable Cores	p. 4
Virtualization within a Parallel Array of Homogeneous Processing Units	p. 17
Feasibility Study of a Self-healing Hardware Platform	p. 29
Applications 1
Application-Specific Signatures for Transactional Memory in Soft Processors	p. 42
Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems	p. 55
Parametric Encryption Hardware Design	p. 68
A Reconfigurable Implementation of the Tate Pairing Computation over GF(2m)	p. 80
Architectures 2
Application Specific FPGA Using Heterogeneous Logic Blocks	p. 92
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip	p. 110
A Dedicated Reconfigurable Architecture for Finite State Machines	p. 122
MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment	p. 134
Applications 2
An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme	p. 145
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs	p. 157
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods	p. 169
Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA	p. 182
Design Tools 1
3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices	p. 194
TROUTE: A Reconfigurability-Aware FPGA Router	p. 207
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing	p. 219
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture	p. 231
Design Tools 2
Design Automation for Reconfigurable Interconnection Networks	p. 244
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures	p. 257
QUAD-A Memory Access Pattern Analyser	p. 269
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations	p. 282
Applications 3
Reconfigurable Computing and Task Scheduling for Active Storage Service Processing	p. 294
A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems	p. 306
A Modified Merging Approach for Datapath Configuration Time Reduction	p. 318
Posters
Reconfigurable Computing Education in Computer Science	p. 329
Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations	p. 337
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing	p. 343
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures	p. 351
A GMM-Based Speaker Identification System on FPGA	p. 358
An FPGA-Based Real-Time Event Sampler	p. 364
A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster	p. 372
An Analysis of Delay Based PUF Implementations on FPGA	p. 382
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor	p. 388
FPGA Implementation of QR Decomposition Using MGS Algorithm	p. 394
Memory-Centric Communication Architecture for Reconfigurable Computing	p. 400
Integrated Design Environment for Reconfigurable HPC	p. 406
Architecture-Aware Custom Instruction Generation for Reconfigurable Processors	p. 414
Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies	p. 420
Towards a Tighter Integration of Generated and Custom-Made Hardware	p. 426
Pipelined Microprocessors Optimization and Debugging	p. 435
Author Index	p. 445
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