"Written for systems engineers, architects, and product managers involved in the planning process for a transition to Serial ATA, this book will contribute to a better understanding of this new interconnect technology. Answered are questions such as why make the change, what problems does serial ATA solve, what potential problems could Serial ATA create and how can they be avoided, and how to transition systems from Parallel ATA or SCSI to Serial ATA. Topics include PHY signaling and interface states, protocol encoding, programming model, flow control, performance, legacy compatibility, enclosure management, signal routing, hot=plug, presence detect, and cable/connector standards. Insights are also provided on the goals driving the Serial ATA standard development, the advantages Serial ATA provides for OEMs, IHVs, and end-users, and how to design and build real-world systems that use Serial ATA."

Knut Grimsrud is the Intel principal engineer for definition of Serial ATA 1.0 and Serial ATA II. He was the technical working group chairman during the Serial ATA 1.0 definition effort and continues to be Intel's technical lead for ongoing Serial ATA definition work. Knut holds a PhD in electrical and computer engineering Hubbert Smith is a Program Manager with Intel's Platform Networking Group

Acknowledgements	p. xiii
The Mission of Serial ATA	p. 1
About the Industry Specification	p. 1
Why Not Continue with Parallel ATA?	p. 2
What about Other Alternatives?	p. 3
The Bottom Line: Software Compatibility	p. 3
Fundamental Goals of the Serial ATA Specification	p. 4
Lower Voltages Required	p. 4
Provide a 10-year Performance Roadmap	p. 4
Lower the Pin Count for Both Host and Devices	p. 6
Hot Docking Devices	p. 8
Easy Device Installation and Configuration	p. 9
Improved Cables and Connectors	p. 9
Software Compatibility with Parallel ATA	p. 10
Cost Competitive with Equivalent Solutions	p. 10
Summary	p. 10
The Serial ATA Transition	p. 13
Removing Barriers to Transition and Adoption	p. 14
Software Compatibility	p. 14
Cost	p. 16
Cost of the Device	p. 16
Cost of the Cable	p. 17
Cost of Serial ATA in PC Motherboards	p. 17
Cost of Serial ATA in Servers	p. 17
Costs of Serial ATA in Laptops	p. 17
Dynamics of Adoption between PCs, Laptops, and Servers	p. 18
Summary	p. 18
Serial ATA Feature Comparison	p. 21
Comparing Serial ATA to Parallel ATA	p. 22
Interface Speed	p. 22
Interface Topology	p. 22
Form Factor	p. 25
Parallel ATA Command Overlap and Queuing	p. 26
Cyclic Redundancy Check (CRC)	p. 26
Hot Dock	p. 27
Comparing Serial ATA to SCSI and Fibre Channel	p. 27
Interface Speed	p. 27
Interface Bus Topology	p. 28
Command Queuing	p. 28
Summary	p. 29
Serial ATA beyond Desktops	p. 31
Building on the Desktop or Desk-side Design	p. 32
Serial ATA in Laptop Computers	p. 33
The Laptop Internal Disk	p. 34
The Laptop Swap Bay	p. 34
Laptop Docking Station	p. 35
Serial ATA in Servers	p. 35
Serial ATA and RAID	p. 37
Reviewing the Server Storage Recipe	p. 40
Summary	p. 40
Architectural Overview	p. 41
Specification Scope	p. 41
Compliment (not replace) Existing Parallel ATA Standards	p. 41
Specify Interoperability, Leave Room for Creative Products	p. 42
Architectural Overview and Block Diagram	p. 44
Topology	p. 45
Architectural Comparison with Parallel ATA	p. 48
Taskfile Architecture	p. 49
DMA Architecture	p. 51
PIO Architecture	p. 51
Master/Slave and Emulation	p. 51
Native Mode	p. 53
Device Discovery	p. 54
Communication Architecture	p. 57
Summary	p. 59
Cables, Connectors, and Backplanes	p. 61
Requirements and Use Cases	p. 61
PC with Disk Drives	p. 62
Laptop Internal, Swap Bay, and Docking Station	p. 63
Server with Directly Attached Internal Storage	p. 65
Directly Attached External Storage, Just a Bunch of Disks (JBOD)	p. 66
The Serial ATA Data Cable Assembly and Receptacle	p. 67
Locations of Connectors on Devices	p. 67
Serial ATA Power Connector	p. 68
Physical Mating	p. 68
Industry Specification for Pin Assignments	p. 69
Hot-Plugging Capability	p. 71
Electrical Characteristics of the Mating Sequence	p. 71
Insertion Speed	p. 71
Cord Construction Example	p. 72
Backplanes and Controller-to-Backplane Connector	p. 73
Summary	p. 75
Physical Layer	p. 77
Low-Voltage Differential Signaling	p. 78
Improved Noise and Crosstalk Immunity	p. 78
Improved EMI	p. 79
Improved Ground Offset Immunity	p. 80
Reduced Power Dissipation	p. 80
Signaling Voltages	p. 81
OOB Signaling	p. 84
Phy Initialization State Machine	p. 87
Normal Initialization	p. 88
Calibration	p. 93
Accommodation for Ceramic Oscillators	p. 94
Speed Negotiation	p. 96
Hot Plugging	p. 98
Alignment	p. 99
ALIGN Primitive	p. 99
Data Recovery and Oversampling Elasticity	p. 101
Tracking	p. 102
Oversampling	p. 102
Managing Frequency Mismatches between Transmitters and Receivers	p. 103
Spread Spectrum Clocking	p. 105
Summary	p. 108
Power Management	p. 109
Power Management in Mobile and Desktop Systems	p. 110
Fine-Grained Management	p. 112
Biodirectional Management	p. 114
Interface Power States and Exit Latencies	p. 114
Interface Power Management Protocol	p. 116
Link Layer Entry Signaling Protocol	p. 116
Phy Layer Exit Signaling Protocol	p. 117
Device Removal during Power Management	p. 119
Summary	p. 120
Link Layer Encoding and Primitives	p. 123
Run Length, 8b/10b Encoding, and DC Balance	p. 124
Primitives	p. 130
Decode Error Propagation	p. 131
Summary	p. 133
Link Layer Protocol	p. 135
Primitives and Basic Services	p. 137
CONT Primitive	p. 137
Signaling Latency	p. 139
CRC Calculation	p. 140
Data Scrambling	p. 140
Protocol	p. 141
Idle Protocol	p. 142
Transmit Protocol	p. 143
Receive Protocol	p. 146
Power Management Protocol	p. 148
PhyRdy and SYNC Escape	p. 149
Summary	p. 150
Transport Layer Frames and Data Structures	p. 153
FIS Structure	p. 154
Register FIS	p. 158
Data FIS	p. 161
DMA Activate FIS	p. 163
PIO Setup FIS	p. 164
Set Device Bits FIS	p. 166
DMA Setup FIS	p. 168
BIST Activate FIS	p. 169
Summary	p. 171
Transport Layer Protocol	p. 173
Host State Machine	p. 174
Host Idle State	p. 174
FIS Transmission	p. 177
FIS Reception	p. 179
Device State Machine	p. 184
Device Idle State	p. 184
FIS Transmission	p. 186
Summary	p. 188
Command Layer Protocol	p. 189
ATA Command Classes	p. 190
Reset and Diagnostics Protocols	p. 191
Hard Reset Protocol	p. 191
Software Reset Protocol	p. 192
Execute Device Diagnostics Protocol	p. 193
Device Reset Protocol	p. 194
Mainstream Command Protocols	p. 195
Non-data Protocol	p. 195
PIO Data-in Protocol	p. 197
PIO Data-out Protocol	p. 199
DMA Data-in Protocol	p. 201
DMA Data-out Protocol	p. 201
Packet Protocol	p. 203
Queued Command Protocols	p. 206
Read DMA Queued Protocol	p. 206
Write DMA Queued Protocol	p. 209
Idle Protocol	p. 210
Summary	p. 212
Serial ATA Implementations and Use Cases	p. 213
Basic Server with Direct Attached Storage	p. 213
Serial ATA with External Simple JBOD	p. 215
Serial ATA with Active JBOD	p. 216
Network Attached Storage	p. 217
Storage Area Network	p. 218
Port Multiplier to Connect More Devices	p. 221
Eliminate Single Points of Failure	p. 222
Eliminating Single Points of Failure with Fail-over	p. 223
Summary	p. 224
Software Considerations	p. 225
Superset Registers	p. 225
SStatus Register	p. 226
SError Register	p. 228
SControl Register	p. 231
Device Presence Detection	p. 232
Reset Race Condition	p. 234
Hot-Plug Detection and Control	p. 234
Transfer Mode Step-Down and PIO Fallback	p. 236
Communications Rate Control	p. 238
Hard Reset	p. 239
Identify Device	p. 239
Error Detection	p. 241
Summary	p. 243
First-Party Direct Memory Access	p. 245
ATA DMA Model	p. 246
First-Party DMA Model	p. 249
Mapping Buffer ID to Host Memory Address	p. 250
Implementation Considerations	p. 252
Software Assisted Implementation	p. 253
Applications	p. 256
Native Command Queuing (Serial ATA II)	p. 257
Summary	p. 259
Testing and Interoperability	p. 261
The Relationship between Testing and the Quality Process	p. 261
System-Level Testing	p. 264
System Level Test Blocks	p. 267
Out of Band and Signal Quality Testing	p. 280
Out of Band Signaling Test	p. 280
Receiver, or Far-End Signal Quality Test	p. 283
Loopback Testing and BIST	p. 285
Summary	p. 288
Protocol Efficiency and Reliability	p. 289
Protocol Efficiency	p. 289
Parallel ATA Protocol Efficiency	p. 291
Serial ATA Protocol Efficiency	p. 292
Data Integrity	p. 295
Estimation	p. 297
Summary	p. 298
The Future of Serial ATA	p. 299
Broad Industry Move From Parallel to Serial	p. 300
The Future Serial ATA Data Rate	p. 302
Connectivity and More Ports	p. 303
Cabling, Connectors, and Backplanes	p. 304
Protocols	p. 304
Miscellaneous	p. 305
Concluding Comments on the Future of Serial ATA	p. 305
8b/10b and 10b/8b Encoding Tables	p. 307
Serial ATA Primitives	p. 341
References	p. 345
Glossary	p. 347
Index	p. 351
Table of Contents provided by Ingram. All Rights Reserved.

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