Soc Design Methodologies: Ifip Tc10/Wg10.5 Eleventh International Conference on Very Large Scale Integration of Systems-On-Chip (Vlsi-Soc'01), December 3-5, 2001, Montpellier,

by Robert, Michel; Rouzeyre, Bruno; Piguet, Christian; Flottes, Marie-Lise; Robert, Michel

• ISBN13: 9781402071485
• ISBN10: 1402071485
• Format: Hardcover
• Copyright: 2002-07-01
• Publisher: Kluwer Academic Pub

Summary

The current trend towards the realization of complex Systems On Chips (SOCs) required the combined efforts and attention of experts in a wide range of areas including embedded hardware/software systems, specific IP cores, reconfigurable architectures, signal and image processing architectures, low power design techniques, design methods and CAD tools, test and verification, modeling, timing issues. Thus the papers presented herein address a wide range of SOC design topics. SOC Design Methodologies comprises a selection of the best papers presented at VLSI-SOC'01, the Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip, which was sponsored by the International Federation for Information Processing (IFIP) Technical Committee 10 / Working Group 10.5, and held in Montpellier, France in December 2001.This volume is essential reading for researchers working on microelectronics system integration, design, and CAD of integrated circuits and systems on chips.

Table of Contents

Preface	ix
Conference Committees	xiii
Architecture for Signal & Image Processing
Two ASIC for Low and Middle Levels of Real Time Image Processing	3	(12)
P. Lamaty
B. Mazar
D. Demigny
L. Kessal
M. Karabernou
64 x 64 Pixels General Purpose Digital Vision Chip	15	(12)
T. Komuro
M. Ishikawa
A Vision System on Chip for Industrial Control	27	(12)
E. Senn
E. Martin
Fast Recursive Implementation of the Gossip Filter	39	(12)
D. Demigny
L. Kessal
J. Pons
Dynamically Re-configurable Architectures
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals	51	(12)
R. David
D. Chillet
S. Pillement
O. Sentieys
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications	63	(12)
G. Sassatelli
L. Torres
P. Benoit
G. Cambon
M. Robert
J. Galy
Reconfigurable Architecture Using High Speed FPGA	75	(12)
L. Kessal
R. Bourguiba
D. Demigny
N. Boudouani
M. Karabernou
CAD Tools
Design Technology for Systems-on-Chip	87	(10)
R. Camposano
D. MacMillen
Distributed Collaborative Design over Cave2 Framework	97	(12)
L. S. Indrusiak
J. Becker
M. Glesner
R. Reis
High Performance Java Hardware Engine and Software Kernel for Embedded Systems	109	(12)
M. H. Miki
M. Kimura
T. Onoye
I. Shirakawa
An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures	121	(12)
J. C. Otero
F. R. Wagner
Interconnect Capacitance Modelling in a VDSM CMOS Technology	133	(12)
D. Bernard
C. Landrault
P. Nouet
IP Design & Reuse
Abstract Communication Model and Automatic Interface generation for IP Integration in Hardware/Software Co-design	145	(12)
C. Araujo
E. Barros
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms	157	(12)
G. Ascia
V. Catania
M. Palesi
Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 μm Bulk and Silicon-On-Insulator CMOS Technologies	169	(12)
A. Neve
D. Flandre
High Level Design Methodologies
A Standardized Co-simulation Backbone	181	(12)
B. A. De Mello
F. R. Wagner
Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory	193	(12)
S. Meftali
F. Gharsalli
F. Rousseau
A. A. Jerraya
Power Issues
Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model	205	(12)
C.H. Gebotys
R. Muresan
Power Consumption Model for the DSP OAK Processor	217	(12)
P. Guitton-Ouhamou
C. Belleudy
M. Auguin
Design for Specific Constraints
Integration of Robustness in the Design of a Cell	229	(12)
J.M. Dutertre
F.M. Roche
G. Cathebras
Impact of Technology Spreading on MEMS design Robustness	241	(12)
V. Beroulle
L. Latorre
M. Dardalhon
C. Oudea
G. Perez
F. Pressecq
P. Nouet
Architectures
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation	253	(12)
N. Roma
L. Sousa
Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder	265	(12)
S. M. Pisuk
P. H. Wu
Low Power, Low Voltage
Low-Voltage Embedded-RAM Technology: Present and Future	277	(12)
K. Itoh
H. Mizuno
Low-Voltage 0.25 μm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors	289	(12)
B. Curran
M. Gifaldi
J. Martin
A. Buyuktosunoglu
M. Margala
D. Albonesi
Gate Sizing for Low Power Design	301	(12)
P. Maurine
N. Azemard
D. Auvergne
Timing Issues
Modeling and Design of Asynchronous Priority Arbiters for on-Chip Communication Systems	313	(12)
J-B. Rigaud
J. Quartana
L. Fesquet
M. Renaudin
Feasible Delay Bound Definition	325	(12)
N. Azemard
M. Aline
P. Maurine
D. Auvergne
Advance in Mixed Signal
CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors	337	(12)
J. H. Choi
S. Bampi
A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor	349	(12)
C. Lallement
F. Pecheux
Y. Herve
Verification & Validation
Speeding Up Verification of RTL Designs by Computing one-to-one Abstractions with Reduced Signal Widths	361	(14)
P. Johannsen
R. Drechsler
Functional Test Generation using Constraint Logic Programming	375	(14)
Z Zeng
M. Ciesielski
B. Rouzeyre
Test
An Industrial Approach to Core-Based System Chip Testing	389	(12)
E. J. Marinissen
Power-Constrained Test Scheduling for SoCs Under a ``no session'' Scheme	401	(12)
M-L. Flottes
J. Pouget
B. Rouzeyre
Random Adjacent Sequences: An Efficient Solution for Logic BIST	413	(12)
R. David
P. Girard
G Landrault
S. Pravossoudovitch
A. Virazel
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST	425	(12)
F. Azais
S. Bernard
Y. Bertrand
M. Renovell
Built-in Test of Analog Non-Linear Circuits in a SOC Environment	437	(12)
L. Carro
A. C. Nacul
D. Janner
M. Lubaszewski
Sensors
Design of a Fast CMOS APS Imager for High Speed Laser Detections	449	(12)
B. Casadei
J. P. Le Normand
Y. Hu
B. Cunin
Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing	461	(12)
V. Beroulle
Y. Bertrand
L. Latorre
P. Nouet
Authors Index	473	(2)
Keywords Index	475