Static Crosstalk-noise Analysis

by Chen, Pinhong; Kirkpatrick, Desmond A.; Keutzer, Kurt William

• ISBN13: 9781402080913
• ISBN10: 1402080913
• Format: Hardcover
• Copyright: 2004-05-31
• Publisher: Kluwer Academic Pub

Summary

As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis.

Table of Contents

List of Figures

List of Tables

Preface1

Introduction

Motivation

Process Trends

CMOS Circuitry

Background and Crosstalk Effects

Static Timing Analysis

Crosstalk Effects

Functional Failure

Timing Variation

Search Space Pruning

Spatial Pruning

Electrical Pruning

Temporal Pruning

Functional Pruning

Problem Complexity v.s. Accuracy

Overview 2: Miller Factor Computation for Coupling Delay

Introduction

Gate Driving and Coupling Model

Nonlinearity of Driver Model

Driver Modeling

Decoupling Approximation

Coupling Model

Bounds

Simple Iterative Approach

Convergence of the Simple Iterative Approach

Newton-Raphson Iteration for Miller Factor

Multiple Miller Factors for Multiple Coupling Nets

Slew Rate (Transition Time) Calculation

Nonzero Initial Voltage Correction

Glitch Waveform Approximation

Experimental Results

Review of Conservativism

Conclusion3: Convergence of Switching Window Computation

Introduction

Background

Simple Upper and Lower Bounds for Switching Windows

Fixed Point Computation

Formulation

Fixed Point Iteration for Switching Windows Computation

Multiple Convergence Points and Unstable Fixed Point

Tightening Bounds

Coupling Models

Noise Calculation Model

Switching Windows Overlapping Model

Discontinuity in Discrete Models

Error Bound between Discrete and Continuous Models

Non-Monotone Property

Convergence of Switching Windows Computation

Proof of Convergence

Computational Complexity

Convergence Rate

Least Evaluation of Coupling RC Networks

Speed-up of Convergence

Conclusion4: Speeding-Up Switching Window Computation

Introduction

Background and Definitions

Piecewise Linear Waveform

Multiple Aggressor Alignment Problem

Coupling Delay Computation in Presence of Crosstalk Noise

Algorithm

Convergence of Our Algorithm

Properties of Our Algorithm

Event Pruning

Scheduling Technique

Experimental Results

Review of Conservativism

Conclusion5: Refinement of Switching Windows

Introduction

Formulation and Algorithm

Arrival Time Uncertainty in Interconnect

Switching Window Density

Input Timing Uncertainty

Complexity

Implementation Consideration

Resolution and Truncation Errors

Experimental Results

Consideration of Slew Rates

Property of Time Slots and Conservativism

Conclusion6: Functional Crosstalk Analysis

Introduction

Approaches and Related Work

Vector Pair Searching Algorithm

Overview

BCOP: Boolean Constrained Optimization Problem

Constructing Circuit via SAT

Maximum Noise under the Zero-Delay Model

Fixed Delay Circuit Construction via SAT

Using Timed Boolean Variables

Translation of Maximum Coupling Effects into an Objective Function

Boolean Constrained Optimization

Discrete Required Time Analysis

Structural Hashing

Coarse Quantum Time

Boolean Constraint Relaxation

Experimental Results

Future Work

Conservativism Consideration

Conclusions

References

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