Stress-Induced Phenomena in Metallization: Eleventh International Workshop on Stress-Induced Phenomena in Metallization

by Zschech, Ehrenfried; Ogawa, Shinichi; Ho, Paul S.

• ISBN13: 9780735408555
• ISBN10: 0735408556
• Format: Hardcover
• Copyright: 2010-12-20
• Publisher: Amer Inst of Physics

Summary

One current challenge to micro- and nanoelectronics is the understanding of stress-related phenomena in metallization. Stresses arising in on-chip and 3D metal interconnects and in the surrounding materials due to thermal mismatch, microstructure changes or process integration as well as electromigration can lead to degradation and failure of microelectronic products. The implementation of low dielectric constant materials into the inlaid copper backend-of-line process has brought new challenges for process integration and reliability. Understanding stress-related phenomena in new materials used for 3D integration and packaging, particularly using through silicon vias and microbumps, is critical for future microelectronic products. The Proceedings summarize new research results and advances in basic understanding of stress-induced phenomena in metallization. In addition to experimental studies, modelling and simulation capabilities are demonstrated to evaluate the effect of stress on product performance and reliability. Stress-related phenomena in 3D IC interconnects are covered too.

Table of Contents

Preface	p. ix
Conference Photograph	p. xi
Copper Interconnects: Microstructure and Interfaces
Grain Size and Cap Layer Effects on Electromigration Reliability of Cu Interconnects: Experiments and Simulation	p. 3
Impact of Surface and Grain Boundary Scattering on the Resistivity of Nanometric Cu Interconnects	p. 12
Improved Interconnect Properties for Nano-Twinned Copper: Microstructure and Stability	p. 23
Micro-Scale Evaluation of Interface Strength on the Patterned Structures in LSI Interconnects	p. 33
Conical Dark-Field Analysis for Small Grain Characterization in Narrow Cu Interconnect Structures: Potential and Challenges	p. 39
Electron Backscattered Diffraction Analysis of Narrow Copper Interconnects in Cross-View to Investigate Scale Effect on Microstructure	p. 47
Sub-100NM Metal Interconnects
Effect of Impurity on Cu Electromigration	p. 57
Stress Phenomena in Times of Porous Low-K Dielectrics	p. 68
Investigation of Stress-Induced Voiding of Double Cross-Shaped Single via Test Structure and Derivatives for Deep-Sub Micron Technology Nodes	p. 78
Influence of the Activation Energy of the Different Migration Effects on Failure Locations in Metallization	p. 85
Application of Ti-Based Self-Formation Barrier Layers to Cu Dual-Damascene Interconnects	p. 91
Growth of Single Crystalline Copper Nanowhiskers	p. 98
Advanced Stress Characterization Techniques
Quality Control on Strained Semiconductor Devices	p. 109
Advanced Stress, Strain and Geometrical Analysis in Semiconductor Devices	p. 114
A New Methodology for In-Situ Residual Stress Measurement in MEMS Structures	p. 120
fibDAC Stress Relief-A Novel Stress Measurement Approach for BEoL Structures	p. 127
Design and Application of a Sensor to Monitor Stress in Deep Submicron Copper Interconnects	p. 133
Strain Determination Using Electron Backscatter Diffraction	p. 139
Mechanical Properties of Materials
Assessment of Mechanical Properties of Nanoscale Structures for Microprocessor Manufacturing	p. 147
Optimization of Dielectric and Elastic Properties of Nanoporous Ultralow-K Dielectric Materials	p. 153
Cohesive Toughness of Low-k Film with Periodically Changing Elastic Modulus: Cube-Corner Indentation	p. 159
Mechanical Solder Characterisation under High Strain Rate Conditions	p. 166
Time and Temperature Dependent Micromechanical Properties of Solder Joints for 3D-Package Integration	p. 176
3D Integration and Packaging: Materials and Reliability
Thermomechanical Reliability Challenges for 3D Interconnects with Through-Silicon Vias	p. 189
3D IC TSV-Based Technology: Stress Assessment for Chip Performance	p. 202
Elimination of the Axial Deformation Problem of Cu-TSV in 3D Integration	p. 214
Sub-Imaging Techniques for 3D-Interconnecte on Bonded Wafer Pairs	p. 221
Effect of Microstructure on Electromigration in Pb-Free Solder Interconnect	p. 229
Damage Induced in Interconnect Structures Mimicking Stresses during Flip Chip Packaging	p. 238
Microstructure Characterization of Lead-Free Solders Depending on Alloy Composition	p. 245
Author Index	p. 255
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