Systematic Design for Optimisation of Pipelined Adcs

by Goes, Joao; Vital, Joao C.; Franca, Jose

• ISBN13: 9780792372912
• ISBN10: 0792372913
• eBook ISBN(s): 9780306481932
• Format: Hardcover
• Copyright: 2001-04-01
• Publisher: Kluwer Academic Pub
• More Book Details
• Purchase Benefits

Summary

Systematic Design for Optimisation of Pipelined ADCs proposes and develops new strategies, methodologies and tools for designing low-power and low-area CMOS pipelined A/D converters. The task is tackled by following a scientifically-consistent approach. First of all, the state of the art in pipeline A/D converters is analysed with a double purpose: a) to identify the best suited among different strategies reported in literature and taking into account the objectives pursued; b) to identify the drawbacks of these strategies as a basic first step to improve them. Then, the book proposes a top-down design approach for implementing high-performance low-power and low-area CMOS pipelined A/D converters through: The conception, development and implementation of self-calibrated techniques to extend the linearity of some critical stages in the architecture of pipelined ADCs. The detailed analysis and modelling of some major non-idealities that limit the physical realisation of pipelined ADCs and the proposal, development and implementation of design methodologies to support systematic design of optimised instances of these converters which combine maximum performance with minimum power dissipation and minimum area occupation. £/LIST£ Several implementations together with consistent measured results are presented. In particular, a practical realisation of a low-power 14-bit 5MS/s CMOS pipelined ADC with background analogue self-calibration is fully described. The proposed approach is fully in line with the best practice regarding the design of mixed-signal integrated circuits. On the one hand, drawbacks of currently existing solutions are overcame through innovative strategies and, on the other hand, the expert knowledge is packaged and made available for re-usability by the community of circuit designers. Finally, feasibility of the strategies and the associated encapsulated knowledge is granted through experimental validation of working silicon. Systematic Design for Optimisation of Pipelined ADCs serves as an excellent reference for analogue design engineers especially designers of low-power CMOS A/D converters. The book may also be used as a text for advanced reading on the subject.

Table of Contents

Contents	v
Abbreviations	ix
Acknowledgements	xi
Preface	xiii
Introduction	1	(6)
Motivation and Context	1	(3)
Goals	4	(3)
General Design Considerations in Pipelined A/D Converters	7	(26)
Introduction	7	(1)
Performance Parameters in Nyquist A/D Converters	7	(8)
Static Parameters	9	(1)
Offset, full-scale and gain errors	9	(1)
Integral Non-Linearity and Differential Non-linearity errors	10	(1)
Dynamic Parameters	11	(1)
Signal-to-Noise Ratio	12	(1)
Total Harmonic Distortion	12	(1)
Spurious Free Dynamic Range	13	(1)
Signal-to-Noise plus Distortion Ratio	13	(1)
Effective Number of Bits and Effective Resolution Bandwidth	13	(1)
Dynamic DNL and INL	14	(1)
Main Non-Idealities in Pipelined A/D Converters	15	(9)
Non-Idealities in the Flash Quantizers	18	(2)
Residue Amplification Gain-Error in the Mdacs	20	(1)
Non-Linearity Errors in the Mdacs	21	(1)
Thermal Noise	22	(1)
Jitter Noise	22	(1)
Aliasing	23	(1)
Overview and Comparison of Published Works in Pipelined A/D Converters	24	(4)
Figures-of-Merit	24	(2)
Discussion	26	(2)
Conclusions	28	(5)
Analogue Code-By-Code Self-Calibration Technique	33	(22)
Introduction	33	(1)
System Architecture	34	(3)
Block Diagram	34	(1)
Mdac and Errors to be Calibrated	35	(2)
The Self-Calibration Technique	37	(5)
Calibration of the Gain Error of the Mdac	37	(1)
Calibration of the Non-Linearity Errors of the Mdac	38	(2)
Conversion Mode	40	(1)
Calibration of the Full-Scale and Offset Errors of the Refdac	41	(1)
Integrated Mdac Prototype and Measured Results	42	(5)
Behavioural System Simulations of a High-Resolution Pipelined Adc	47	(5)
Conclusions	52	(3)
Systematic Design Methodology for Optimisation of High-Speed Self-Calibrated Pipelined Adcs	55	(28)
Introduction	55	(1)
Architecture Description	56	(3)
Design Considerations	59	(7)
Thermal Noise Constraints	60	(2)
Ota Requirements in the Mdac	62	(1)
Specifications for the on-Resistance of the Switches in the Mdac	63	(1)
Specifications for the Flash Quantizer	64	(1)
Self-Calibration Requirements	65	(1)
Power and Area Estimation	66	(3)
Power Estimation	66	(2)
Area Estimation	68	(1)
Optimisation	69	(3)
Methodology	69	(2)
Distribution of the Noise Contributions in the Pipeline	71	(1)
Design Example	72	(5)
Conclusions	77	(6)
Design of a 14-Bit 5 MS/S Cmos Pipelined A/D Converter	83	(46)
Introduction	83	(1)
Specifications, Architecture Definition and Background Self-Calibration of the Overall Conversion System	84	(3)
Specifications	84	(1)
Architecture	84	(1)
On-The-Fly Background Calibration Concept	85	(2)
Design of the Basic Building Blocks	87	(36)
Design of the 8-Bit 5MS/S Backend Adc	87	(1)
The 1.5-bit Mdac	88	(4)
The 1.5-bit Flash Quantizer	92	(3)
Design of the 7-Bit 5MS/S Front-End Adc	95	(1)
The Front-end Sample-and-Hold	95	(4)
The 4-bit Mdac	99	(4)
The 4-bit Flash Quantizer	103	(4)
The Refdac	107	(3)
The 12-bit Caldac	110	(5)
The High Accuracy Comparator	115	(2)
The Reference Buffering Circuitry	117	(3)
Biasing Circuitry	120	(1)
The Non-Overlapping Clock generators	120	(2)
Design of the Digital Building Blocks	122	(1)
The Digital Correction Logic	122	(1)
The Controller and the Memories	122	(1)
Testing Modes	123	(1)
Design of the Overall System and Functional Simulations	123	(2)
Conclusions	125	(4)
Integrated Prototypes of Pipelined Adcs and Measured Results	129	(18)
Introduction	129	(1)
Integrated Prototype of an 8-Bit 5MS/S Pipelined Adc with Minimum Bit-Per-Stage Architecture	130	(3)
Integrated Prototype of a 14-Bit 5MS/S Background Self-Calibrated Pipelined Adc with a Power/Area Optimised Architecture	133	(10)
Layout Considerations	135	(2)
Measurement Setup	137	(2)
Measured Results	139	(4)
Conclusions	143	(4)
Conclusions	147	(2)
Appendixes	149