Systematic Methodology for Real-Time Cost-Effective Mapping Of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

by Ma, Zhe; Marchal, Pol; Scarpazza, Daniele Paolo; Yang, Pengyuan; Wong, Chun

• ISBN13: 9781402063282
• ISBN10: 1402063288
• Format: Hardcover
• Copyright: 2007-11-03
• Publisher: Springer Verlag

Summary

Systematic methodology for real-time cost-effective mapping of dynamic concurrent task-based systems on heterogeneous platforms gives an overview of the state-of-the-art in system-level design trade-off explorations for concurrent tasks running on embedded heterogeneous multiple processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are concurrent in the sense that multiple subsystems can be running simultaneously. Also, these applications are so dynamic at run-time that the designs based on the worst case execution times are inefficient in terms of resource allocation (e.g., energy budgets). A novel systematical approach is clearly necessary in the area of system-level design for the embedded systems where those concurrent and dynamic applications are mapped. This material is mainly based on research at IMEC and its international university network partners in this area in the period 1997-2006. In order to deal with the concurrent and dynamic behaviors in an energy-performance optimal way, we have adopted a hierarchical system model (i.e., the gray-box model) that can both exhibit the sufficient detail of the applications for design-time analysis and hide unnecessary detail for a low-overhead run-time management. We have also developed a well-balanced design-time/run-time combined task scheduling methodology to explore the trade-off space at design-time and efficiently handle the system adaptations at run-time. Moreover, we have identified the connection between task-level memory/communication management and task scheduling and illustrated how to perform the task-level memory/communication management in order to obtain the design constraints that enable the this connection. A fast approach is also shown to estimate at the system-level, the energy and performance characterization of applications executing on the target platform processors.

Author Biography

Francky Catthoor is a leading researcher at IMEC and is very well established within the EDA community. He is IEEE Fellow and has edited and authored 6 books for Springer/Kluwer.

Table of Contents

Introduction

The System-on-Chip Era

Characteristics of Embedded Software

Context and Motivation

TCM Framework

Overview of Chapters

Related Work

Real-time Scheduling

Low-power Considerations

Platform Issues and Co-design Framework

System Model and Work flow

Overview of TCM Work flow

Gray-box Model

System Scenario Selection

Two-phase Scheduling

Summary

Basic Design-time Scheduling

Problem Formulation

Exact Scheduling Algorithms

Forward Search Algorithm

Backward Search Algorithm

Sub-platform Scheduling

Handling Timing-Constraints

Summary

Scalable Design-time Scheduling

Introduction

Motivational Example

Thread Frame Decomposition

Thread Partition Clustering

Thread Partition Interleaving

Experimental Results and Discussions

Comparison with State of the Art

Summary

Fast and Scalable Run-time Scheduling

Two-Phase Task Scheduling: Why and How

Run-time Scheduling Algorithm

Experimental Results

Summary

Handling of Multi-dimensional Pareto Curves

Overview of The Customized Run-time Management

Problem Formulation of Run-time Operating Point Selector

Related Work

MP-SoC Heuristic Description

Experimental Results

Summary

Run-time Software Multithreading

Motivation of Run-time Re-scheduling

Run-time Interleaving

Experimental Results and Discussion

Comparison with State of the Art

Summary

Fast Source-level Performance Estimation

Introduction

Motivational Example

Comparison With State of The Art

Fundamentals of The Estimation Technique

Experimental Results

Summary

Handling of Task-level Data Communication and Storage

Memory Architecture

Exploring Thread Node Level Data Reuse

Data Assignment On L1 Memory Layer

Bandwidth Aware Scheduling

Handling inter-TN and inter-TF Data Transfers

Summary

Demonstration on Heterogeneous Multiprocessor SoCs

Motivation for Heterogeneous Multiprocessor Platforms

Mapping Visual Texture Coding Decoder

Summary

Conclusions and future research work Input and output data of scheduling examples in

References

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