Timing Analysis and Optimization of Sequential Circuits

by Maheshwari, Naresh; Sapatnekar, Sachin S.

• ISBN13: 9780792383215
• ISBN10: 0792383214
• Format: Hardcover
• Copyright: 1999-02-01
• Publisher: Kluwer Academic Pub

Summary

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: Algorithms for sequential timing analysis Fast algorithms for clock skew optimization and their applications Efficient techniques for retiming large sequential circuits Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.

Table of Contents

List of Figures	ix	(4)
Preface	xiii
1. INTRODUCTION	1	(6)
1.1 Performance Optimization of VLSI Circuits	1	(4)
1.2 Outline of the Book	5	(2)
2. TIMING ANALYSIS OF SEQUENTIAL CIRCUITS	7	(26)
2.1 Introduction	7	(3)
2.2 Combinational Delay Modeling	10	(7)
2.3 Clocking Disciplines: Edge-Triggered Circuits	17	(1)
2.4 Resolving Short Path Violations	18	(2)
2.5 Clocking Disciplines: Level-clocked Circuits	20	(6)
2.6 Clock Schedule Optimization for Level-Clocked Circuits	26	(1)
2.7 Timing Analysis of Domino Logic	27	(4)
2.8 Concluding Remarks	31	(2)
3. CLOCK SKEW OPTIMIZATION	33	(32)
3.1 The Notion of Deliberate Clock Skew	33	(2)
3.2 Is Clock Skew Optimization Safe?	35	(1)
3.3 Clock Tree Construction	35	(5)
3.4 Clock Skew Optimization	40	(6)
3.5 Clock Skew Optimization with Transistor Sizing	46	(14)
3.6 Wave Pipelining Issues	60	(2)
3.7 Deliberate Skews for Peak Current Reduction	62	(1)
3.8 Conclusion	63	(2)
4. THE BASICS OF RETIMING	65	(34)
4.1 Introduction to Retiming	65	(4)
4.2 A Broad Overview of Research on Retiming	69	(3)
4.3 Modeling and Assumptions for Retiming	72	(2)
4.4 Minperiod Optimization of Edge-triggered Circuits	74	(14)
4.5 Level-clocked Circuits	88	(9)
4.6 Concluding Remarks	97	(2)
5. MINAREA RETIMING	99	(24)
5.1 The Leiserson-Saxe Approach	100	(5)
5.2 The Minaret Algorithm	105	(8)
5.3 Minarea Retiming of Level-Clocked Circuits	113	(10)
6. RETIMING CONTROL LOGIC	123	(24)
6.1 Minperiod Initial State Retiming via the State Transition Graph	124	(3)
6.2 Minperiod Initial State Retiming via Reverse Retiming	127	(2)
6.3 Minarea Initial State Retiming	129	(15)
6.4 Maintaining Initial States With Explicit Reset Circuitry	144	(3)
7. MISCELLANEOUS ISSUES IN RETIMING	147	(22)
7.1 Retiming and Testing	148	(6)
7.2 Verification Issues	154	(2)
7.3 Retiming for Low Power	156	(1)
7.4 Retiming with Logic Synthesis	157	(4)
7.5 Retiming for FPGA's	161	(1)
7.6 Practical Issues	162	(6)
7.7 Conclusion	168	(1)
8. CONCLUSION	169	(2)
References	171