Transactions on High-performance Embedded Architectures and Compilers I

by Stenstrom, Per; O'Boyle, Michael; Bodin, Francois; Cintra, Marcelo; Mckee, Sally A.

• ISBN13: 9783540715276
• ISBN10: 3540715274
• Format: Paperback
• Copyright: 2007-05-18
• Publisher: Springer Verlag

Summary

Transactions on HiPEAC is a new journal which aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This inaugural issue contains 21 papers - headed by an article by Sir Maurice Wilkes, who provides a perspective on the exciting evolution of computers to the present day. Reflecting on the evolution in computer architecture over the last decades, he also provides his outlook on the forces that will be important for developments over the next decade. The second regular paper describes a roadmap put together by the HiPEAC community to mark out the 10 most important research challenges to be faced in the next decade. The volume also includes a part containing the best papers of the 2005 International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2005), a part consisting of papers devoted to the topic of optimizing compilers, as well as a third part containing the best papers on embedded architectures and compilers from the 2006 ACM International Conference on Computing Frontiers.

Table of Contents

Transactions on HiPEAC I
High performance processor chips	p. 1
High-performance embedded architecture and compilation roadmap	p. 5
First international conference on high-performance embedded architectures and compilers, HiPEAC 2005 : best papers
Quick and practical run-time evaluation of multiple program optimizations	p. 34
Specializing cache structures for high performance and energy conservation in embedded systems	p. 54
GCH : hints for triggering garbage collections	p. 74
Memory-centric security architecture	p. 95
Power aware external bus arbitration for system-on-a-chip embedded systems	p. 116
Optimizing compilers
Convergent compilation applied to loop unrolling	p. 140
Finding and applying loop transformations for generating optimized FPGA implementations	p. 159
Dynamic and on-line design space exploration for reconfigurable architectures	p. 179
Automatic discovery of coarse-grained parallelism in media applications	p. 194
An approach for enhancing inter-processor data locality on chip multiprocessors	p. 214
ACM international conference on computing frontiers 2006 : best papers
Hardware/software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology	p. 239
Using application bisection bandwidth to guide tile size selection for the synchroscalar tile-based architecture	p. 259
Static cache partitioning robustness analysis for embedded on-chip multi-processors	p. 279
Selective code compression scheme for embedded systems	p. 298
A prefetching algorithm for multi-speed disks	p. 317
Reconfiguration strategies for environmentally powered devices : theoretical analysis and experimental validation	p. 341
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