Ultra-Low Voltage Nano-Scale Memories

by Itoh, Kiyoo; Horiguchi, Masashi; Tanaka, Hitoshi

• ISBN13: 9780387333984
• ISBN10: 0387333983
• Format: Hardcover
• Copyright: 2007-08-17
• Publisher: Springer Verlag

Summary

Ultra-low voltage large-scale integrated circuits (LSIs) in nano-scale technologies are needed to:-Meet the needs of a rapidly growing mobile cell phone market-Offset a significant increase in the power dissipation of high-end microprocessor units. Low power large capacity memories are a necessary component of low voltage LSIs. Many challenges arise in the process of achieving such memories as their devices and voltages are scaled down below 100nm and sub-1-V. A high signal-to-noise (S/N) ratio design is necessary to deal with small signal voltages from low-voltage memory cells in the presence of large noise sources in a high-density memory-cell array. Moreover, innovative circuits and devices are needed to resolve the increasing problems of leakage currents and variability in both speed and leakage. Since the solutions to these problems lie between different fields, (e.g., digital and analog, SRAM and DRAM) a multidisciplinary approach is needed. Ultra-Low Voltage Nano-Scale Memories is an authoritative monograph that addresses these challenges. This book is written for memory and circuit designers as well as for researchers and students who are interested in ultra-low voltage nano-scale memory LSIs.

Table of Contents

Preface	p. V
An Introduction to LSI Design	p. 1
Introduction	p. 1
Basics of LSI Devices	p. 1
MOST Characteristics	p. 1
Bulk MOSTs	p. 9
SOI MOSTs	p. 11
Resistors	p. 13
Leakage Currents	p. 14
Subthreshold Current	p. 14
Gate-Tunneling Current	p. 16
Substrate Current	p. 17
pn-Junction Current	p. 18
Basics of CMOS Digital Circuits	p. 19
CMOS Inverter	p. 20
NOR and NAND Gates	p. 21
Cross-Coupled CMOS Sense Amplifier	p. 21
Level Shifter	p. 23
Charge Pump	p. 23
Ring Oscillator	p. 24
Basics of CMOS Analog Circuit	p. 24
Analog Circuits compared with Digital Circuits	p. 24
Equivalent Circuits	p. 26
Basic Analog Circuits	p. 29
Basics of Memory LSIs	p. 32
Memory Chip Architectures	p. 34
Memory Cells	p. 35
Basics of DRAMs	p. 37
Read Operation	p. 38
Write Operation	p. 40
Refresh Operation	p. 41
Basics of SRAMs	p. 42
Read Operation	p. 42
Write Operation	p. 44
Basics of Flash Memories	p. 45
The Basic Operation of Rash Memory Cells	p. 45
The NOR Cell	p. 50
The NAND Cell	p. 53
Soft Errors	p. 56
Redundancy Techniques	p. 57
Error Checking and Collecting (ECC) Circuit	p. 59
Scaling Laws	p. 60
Constant Electric-Field Scaling	p. 60
Constant Operation-Voltage Scaling	p. 62
Combined Scaling	p. 63
Power Supply Schemes	p. 63
Trends in Power Supply Voltages	p. 66
Power Management for Future Memories	p. 68
Static Control of Internal Supply Voltages	p. 70
Dynamic Control of Internal Supply Voltages	p. 72
Roles of On-Chip Voltage Converters	p. 73
Ultra-Low Voltage Nano-Scale DRAM Cells	p. 79
Introduction	p. 79
Trends in DRAM-Cell Developments	p. 80
The 1-T Cell and Related Cells	p. 80
Gain Cells	p. 82
1-T-Based Cells	p. 85
The Data-Line Arrangement	p. 85
The Data-Line Precharging Scheme	p. 87
Design of the Folded-Data-Line 1-T Cell	p. 87
The Lowest Necessary V[subscript t] and Word Line Voltage	p. 87
The Minimum V[subscript DD]	p. 91
Signal Charge and Signal Voltage	p. 92
Noise Sources	p. 93
The Effective Signal Voltage and the Gate-Over-Drive of SAs	p. 98
Noise Reduction	p. 101
The Minimum V[subscript DD]	p. 104
Design of the Open-Data-Line 1-T Cell	p. 104
Noise-Generation Mechanism	p. 105
Concepts for Noise Reduction	p. 107
Data-Line Shielding Circuits	p. 110
Design of the 2-T Cell	p. 110
Design of Double-Gate Fully-Depleted SOI Cells	p. 112
Ultra-Low Voltage Nano-Scale SRAM Cells	p. 119
Introduction	p. 119
Trends in SRAM-Cell Developments	p. 120
Leakage Currents in the 6-T SRAM Cell	p. 122
The Voltage Margin of the 6-T SRAM Cell	p. 124
Read and Write Voltage Margin	p. 125
Signal Charge	p. 126
Improvements of the Voltage Margin of the 6-T SRAM Cell	p. 130
Lithographically Symmetric Cell Layout	p. 130
Power-Supply Controlled Cells	p. 131
Fully-Depleted SOI Cells	p. 135
The 6-T SRAM Cell Compared with the 1-T DRAM Cell	p. 139
Cell Operations	p. 139
Flip-Flop Circuits	p. 140
The Minimum V[subscript DD] of RAMs	p. 143
Soft-Error Immunity	p. 146
Memory Cell Size	p. 147
Leakage Reduction for Logic Circuits in RAMs	p. 151
Introduction	p. 151
Basic Concepts for Leakage Reduction of MOSTs	p. 152
Basics of Leakage Reduction Circuits	p. 154
Basic Concepts	p. 154
Comparisons between Reduction Circuits	p. 157
Gate-Source Reverse Biasing Schemes	p. 158
Gate-Source Self-Reverse Biasing	p. 159
Gate-Source Offset Driving	p. 163
Applications to RAMs	p. 166
Leakage Sources in RAMs	p. 167
Features of Peripheral Circuits of RAMs	p. 169
Applications to DRAM Peripheral Circuits	p. 170
Applications to SRAM Peripheral Circuits	p. 176
Variability Issue in the Nanometer Era	p. 183
Introduction	p. 183
V[subscript t] Variation in the Nanometer Era	p. 183
Leakage Variations	p. 184
Speed Variations of Logic Circuits	p. 185
Variations in V[subscript t] Mismatch of Flip-Flop Circuits	p. 186
Solutions for the Reductions	p. 189
Redundancy and ECC	p. 189
Symmetric Layouts for Flip-Flop Circuits	p. 190
Controls of Internal Supply Voltages	p. 190
Raised Power Supply Voltage	p. 192
Fully-Depleted SOI	p. 193
Derivation of maximum V[subscript t] mismatch	p. 193
Reference Voltage Generators	p. 199
Introduction	p. 199
The V[subscript t]-Referenced V[subscript REF] Generator	p. 200
The V[subscript t]-Difference ([Delta]V[subscript t] V[subscript REF] Generator	p. 203
Basic [Delta]V[subscript t] V[subscript REF] Generator	p. 203
Application of [Delta]V[subscript t] V[subscript REF] Generator	p. 206
The Bandgap V[subscript REF] Generator	p. 209
Principle	p. 209
Circuit Design	p. 211
Variation of Reference Voltage	p. 214
The Bandgap V[subscript REF] Generators for Low Supply Voltage	p. 215
The Reference Voltage Converter/Trimming Circuit	p. 218
Basic Design	p. 218
Design for Burn-In Test	p. 219
Layout Design of V[subscript REF] Generator	p. 224
Voltage Down-Converters	p. 231
Introduction	p. 231
The Series Regulator	p. 233
DC Characteristics	p. 234
Transient Characteristics	p. 239
AC Characteristics and Phase Compensation	p. 243
PSRR	p. 262
Low-Power Design	p. 265
Applications	p. 267
The Switching Regulator	p. 269
The Switched-Capacitor Regulator	p. 272
The Half -V[subscript DD] Generator	p. 277
Relationship between Phase Margin and Loop Gain	p. 279
Voltage Up-Converters and Negative Voltage Generators	p. 285
Introduction	p. 285
Basic Voltage Converters with Capacitor	p. 287
Voltage Doublet	p. 287
Negative Voltage Generator	p. 292
Applications to Memories	p. 295
Dickson-Type Voltage Multiplier	p. 300
Voltage Up-Converter	p. 300
Negative Voltage Generator	p. 305
Switched-Capacitor (SC)-Type Voltage Multipliers	p. 307
Voltage Up-Converter and Negative Voltage Generator	p. 307
Fractional Voltage Up-Converters	p. 307
Comparisons between Dickson-Type and SC-Type Multipliers	p. 309
Influences of Parasitic Capacitances	p. 309
Charge Recycling Multiplier	p. 311
Voltage Converters with an Inductor	p. 313
Level Monitor	p. 317
Level Monitor for Voltage Up-Converter	p. 317
Level Monitor for Negative Voltage Multiplier	p. 318
Efficiency Analysis of Voltage Up-Converters	p. 319
Dickson-Type Charge Pump Circuit	p. 319
Switched-Capacitor-Type Charge Pump Circuit	p. 322
High-Voltage Tolerant Circuits	p. 327
Introduction	p. 327
Needs for High-Voltage Tolerant Circuits	p. 327
Concepts of High-Voltage Tolerant Circuits	p. 328
Applications to Internal Circuits	p. 330
Level Shifter	p. 330
Voltage Doubler	p. 332
Applications to I/O Circuits	p. 333
Output Buffers	p. 333
Input Buffers	p. 336
Index	p. 339
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