Verification Techniques for System-Level Design

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  • Format: Hardcover
  • Copyright: 2007-10-17
  • Publisher: Elsevier Science
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The book presents readers with formal and semi-formal verification techniques for high-level design stages of LSI logic designs that drastically improve design productivity. High-level design support is the most critical issue in current digital system designs, and this book covers various aspects of verification issues that occur throughout design processes in C/C++ based languages.

Table of Contents

Acknowledgmentsp. ix
Introductionp. 1
Higher-Level Design Methodology and Associated Verification Problemsp. 5
Introductionp. 5
Issues in High-Level Designp. 6
C/C++-Based Design and Specification Languagesp. 12
SpecC Languagep. 14
The Semantics of par Statementsp. 18
Relationship with Simulation Timep. 21
System-Level Design Methodology Based on C/C++-Based Design and Specification Languagesp. 24
Verification Problems in High-Level Designsp. 28
Basic Technology for Formal Verificationp. 33
The Boolean Satisfiability Problemp. 33
The DPLL Algorithmp. 34
Enhancements to Modern SAT Solversp. 35
Capabilities of Modern SAT Solversp. 38
Binary Decision Diagramsp. 38
Manipulation of BDDsp. 42
Variants of BDDsp. 43
Automatic Test Pattern Generation Enginesp. 44
Single Stuck-at Testing for Combinational Circuitsp. 45
Stuck-at Testing in Sequential Circuitsp. 48
SAT, BDD, and ATPG Engines for Validationp. 49
Theorem-Proving and Decision Proceduresp. 49
Referencesp. 54
Verification Algorithms for FSM Modelsp. 57
Combinational Equivalence Checkingp. 57
Sequential Equivalence Checking as Combinational Equivalence Checkingp. 57
Latch Mapping Problemp. 58
EC Based on Internal Equivalencesp. 61
Anatomy and Capabilities of Modern CEC Toolsp. 64
Model Checkingp. 66
Modeling Concurrent Systemsp. 66
Temporal Logicsp. 66
Types of Propertiesp. 70
Basic Model-Checking Algorithmsp. 70
Symbolic Model Checkingp. 74
Semi-Formal Verification Techniquesp. 83
SAT-Based Bounded Model Checkingp. 83
Symbolic Simulationp. 88
Enhancing Simulation Using Formal Methodsp. 91
Conclusionp. 93
Referencesp. 93
Static Checking of Higher-Level Design Descriptionsp. 101
Program Slicingp. 102
System Dependence Graphp. 104
Nodes and Edgesp. 104
Concurrencyp. 104
Synchronization on Concurrent Processesp. 104
Checking Method and Its Implying Design Flowp. 106
Basic Static Description Checkingp. 108
Improvement of Accuracy Using Conditions of Control Nodesp. 115
Application of the Checking Methods to HW/SW Partitioning and Optimizationp. 129
Case Studyp. 132
MPEG2p. 132
JPEG2000p. 132
Experimental Results on Static Checkingp. 133
Referencesp. 134
Equivalence Checking on Higher-Level Design Descriptionsp. 137
Introductionp. 137
High-Level Design Flow from the Viewpoint of Equivalence Checkingp. 138
Symbolic Simulation for Equivalence Checkingp. 141
Equivalence-Checking Methods Based on the Identification of Differences between two Descriptionsp. 144
Identification of Differences between Two Descriptionsp. 147
Symbolic Simulation Based on Textual Differencesp. 148
Examplep. 150
Experimental Resultsp. 151
Further Improvement on the Use of Differences between Two Descriptionsp. 155
Extension of the Verification Areap. 158
Symbolic Simulation on SDGsp. 159
Verification Examplep. 159
Discussion of the Strategy of Extensionp. 160
Experimental Results on the Extension-Based Methodp. 160
Referencesp. 162
Model Checking on Higher-Level Design Descriptionsp. 163
Introductionp. 163
Goat of Synchronization Verification in High-Level Designsp. 164
Model Checking and High-Level Design Descriptionsp. 167
Brief Review of SpecC and Its Semantics for Synchronization Verificationp. 168
Synchronization Verification Frameworkp. 173
From SpecC to Boolean SpecCp. 175
From Boolean SpecC to Mathematical Representations of Equalities/Inequalitiesp. 176
Verification Methodp. 177
Validating the Abstract Counterexamplep. 179
Checking for Race Conditionsp. 179
Renaming Variablesp. 180
Predicate Discovery and Boolean SpecC Refinementp. 180
Experimental Resultsp. 181
Referencesp. 185
Simulation-Based Verification Techniques for System-Level Designsp. 187
Introductionp. 187
Simulation Typesp. 188
Event-Driven Simulationp. 189
Cycle-Based Simulationp. 190
Specification/Behavior-Level Simulationp. 191
Mixed-Mode Simulationp. 191
High-Level Simulation Toolsp. 193
Static Checking (Linting)p. 193
Simulators, Waveform Viewers, and Debuggersp. 194
Simulation Drawbacksp. 196
Coverage Metricsp. 196
Drawbacks of Coverage Metricsp. 202
Test-Bench Automationp. 204
Transaction Level Modelingp. 204
Property Specification Languagesp. 206
Test-Bench Automation Frameworksp. 208
Model-Driven Automatic Test-Bench Generationp. 209
Automatic Test-Bench Generation from Implementation Designp. 212
Tackling Performance Issuesp. 213
Emulation and Hardware Accelerationp. 214
Using Preverified IPs/Cores and Higher Abstraction Levelsp. 217
Correct by Construction Designp. 218
Stopping Criteriap. 219
An Example Case Studyp. 220
Conclusionp. 228
Future Directionsp. 228
Referencesp. 229
Conclusionp. 231
Indexp. 235
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