The Verilog Hardware Description Language

by Thomas, Donald E.; Moorby, Philip R.

• ISBN13: 9781402070891
• ISBN10: 1402070896
• Edition: 5th
• Format: Hardcover
• Copyright: 2002-06-01
• Publisher: Kluwer Academic Pub

Summary

The standard text for Verilog. Presents the new IEEE 1364-2001 standard of the language with examples that have been updated to illustrate the new features of the language. A valuable resource for engineering students interested in describing, simulating, and synthesizing digital systems.

Table of Contents

Preface	xv
From the Old to the New	xvii
Acknowledgments	xxi
Verilog --- A Tutorial Introduction	1	(34)
Getting Started	2	(9)
A Structural Description	2	(2)
Simulating the binaryToESeg Driver	4	(3)
Creating Ports For the Module	7	(1)
Creating a Testbench For a Module	8	(3)
Behavioral Modeling of Combinational Circuits	11	(3)
Procedural Models	12	(1)
Rules for Synthesizing Combinational Circuits	13	(1)
Procedural Modeling of Clocked Sequential Circuits	14	(7)
Modeling Finite State Machines	15	(3)
Rules for Synthesizing Sequential Systems	18	(1)
Non-Blocking Assignment (``<='')	19	(2)
Module Hierarchy	21	(6)
The Counter	21	(1)
A Clock for the System	21	(1)
Tying the Whole Circuit Together	22	(3)
Tying Behavioral and Structural Models Together	25	(2)
Summary	27	(1)
Exercises	28	(7)
Logic Synthesis	35	(38)
Overview of Synthesis	35	(2)
Register-Transfer Level Systems	35	(1)
Disclaimer	36	(1)
Combinational Logic Using Gates and Continuous Assign	37	(3)
Procedural Statements to Specify Combinational Logic	40	(8)
The Basics	40	(2)
Complications --- Inferred Latches	42	(1)
Using Case Statements	43	(1)
Specifying Don't Care Situations	44	(2)
Procedural Loop Constructs	46	(2)
Inferring Sequential Elements	48	(4)
Latch Inferences	48	(2)
Flip Flop Inferences	50	(2)
Summary	52	(1)
Inferring Tri-State Devices	52	(1)
Describing Finite State Machines	53	(5)
An Example of a Finite State Machine	53	(3)
An Alternate Approach to FSM Specification	56	(2)
Finite State Machine and Datapath	58	(8)
A Simple Computation	58	(1)
A Datapath For Our System	58	(2)
Details of the Functional Datapath Modules	60	(1)
Wiring the Datapath Together	61	(2)
Specifying the FSM	63	(3)
Summary on Logic Synthesis	66	(2)
Exercises	68	(5)
Behavioral Modeling	73	(36)
Process Model	73	(2)
If-Then-Else	75	(7)
Where Does The ELSE Belong?	80	(1)
The Conditional Operator	81	(1)
Loops	82	(4)
Four Basic Loop Statements	82	(3)
Exiting Loops on Exceptional Conditions	85	(1)
Multi-way Branching	86	(5)
If-Else-If	86	(1)
Case	86	(3)
Comparison of Case and If-Else-If	89	(1)
Casez and Casex	90	(1)
Functions and Tasks	91	(11)
Tasks	93	(4)
Functions	97	(3)
A Structural View	100	(2)
Rules of Scope and Hierarchical Names	102	(4)
Rules of Scope	102	(3)
Hierarchical Names	105	(1)
Summary	106	(1)
Exercises	106	(3)
Concurrent Processes	109	(34)
Concurrent Processes	109	(2)
Events	111	(5)
Event Control Statement	112	(1)
Named Events	113	(3)
The Wait Statement	116	(6)
A Complete Producer-Consumer Handshake	117	(3)
Comparison of the Wait and While Statements	120	(1)
Comparison of Wait and Event Control Statements	121	(1)
A Concurrent Process Example	122	(6)
A Simple Pipelined Processor	128	(4)
The Basic Processor	128	(2)
Synchronization Between Pipestages	130	(2)
Disabling Named Blocks	132	(2)
Intra-Assignment Control and Timing Events	134	(2)
Procedural Continuous Assignment	136	(2)
Sequential and Parallel Blocks	138	(2)
Exercises	140	(3)
Module Hierarchy	143	(14)
Module Instantiation and Port Specifications	143	(3)
Parameters	146	(4)
Arrays of Instances	150	(1)
Generate Blocks	151	(3)
Exercises	154	(3)
Logic Level Modeling	157	(38)
Introduction	157	(1)
Logic Gates and Nets	158	(13)
Modeling Using Primitive Logic Gates	159	(3)
Four-Level Logic Values	162	(1)
Nets	163	(3)
A Logic Level Example	166	(5)
Continuous Assignment	171	(5)
Behavioral Modeling of Combinational Circuits	172	(2)
Net and Continuous Assign Declarations	174	(2)
A Mixed Behavioral/Structural Example	176	(4)
Logic Delay Modeling	180	(7)
A Gate Level Modeling Example	181	(1)
Gate and Net Delays	182	(3)
Specifying Time Units	185	(1)
Minimum, Typical, and Maximum Delays	186	(1)
Delay Paths Across a Module	187	(2)
Summary of Assignment Statements	189	(1)
Summary	190	(1)
Exercises	191	(4)
Cycle-Accurate Specification	195	(16)
Cycle-Accurate Behavioral Descriptions	195	(3)
Specification Approach	195	(2)
A Few Notes	197	(1)
Cycle-Accurate Specification	198	(5)
Inputs and Outputs of an Always Block	198	(1)
Input/Output Relationships of an Always Block	199	(3)
Specifying the Reset Function	202	(1)
Mealy/Moore Machine Specifications	203	(6)
A Complex Control Specification	204	(1)
Data and Control Path Trade-offs	204	(5)
Introduction to Behavioral Synthesis	209	(1)
Summary	210	(1)
Advanced Timing	211	(28)
Verilog Timing Models	211	(3)
Basic Model of a Simulator	214	(6)
Gate Level Simulation	215	(1)
Towards a More General Model	215	(3)
Scheduling Behavioral Models	218	(2)
Non-Deterministic Behavior of the Simulation Algorithm	220	(6)
Near a Black Hole	221	(2)
It's a Concurrent Language	223	(3)
Non-Blocking Procedural Assignments	226	(7)
Contrasting Blocking and Non-Blocking Assignments	226	(1)
Prevalent Usage of the Non-Blocking Assignment	227	(1)
Extending the Event-Driven Scheduling Algorithm	228	(3)
Illustrating Non-Blocking Assignments	231	(2)
Summary	233	(1)
Exercises	234	(5)
User-Defined Primitives	239	(12)
Combinational primitives	240	(3)
Basic Features of User-Defined Primitives	240	(2)
Describing Combinational Logic Circuits	242	(1)
Sequential Primitives	243	(3)
Level-Sensitive Primitives	244	(1)
Edge-Sensitive Primitives	244	(2)
Shorthand Notation	246	(1)
Mixed Level- and Edge-Sensitive Primitives	246	(3)
Summary	249	(1)
Exercises	249	(2)
Switch Level Modeling	251	(32)
A Dynamic MOS Shift Register Example	251	(5)
Switch Level Modeling	256	(7)
Strength Modeling	256	(3)
Strength Definitions	259	(1)
An Example Using Strengths	260	(2)
Resistive MOS Gates	262	(1)
Ambiguous Strengths	263	(7)
Illustrations of Ambiguous Strengths	264	(1)
The Underlying Calculations	265	(5)
The miniSim Example	270	(11)
Overview	270	(1)
The miniSim Source	271	(9)
Simulation Results	280	(1)
Summary	281	(1)
Exercises	281	(2)
Projects	283	(10)
Modeling Power Dissipation	283	(3)
Modeling Power Dissipation	284	(1)
What to do	284	(1)
Steps	285	(1)
A Floppy Disk Controller	286	(7)
Introduction	286	(1)
Disk Format	287	(1)
Function Descriptions	288	(3)
Reality Sets In...	291	(1)
Everything You Always Wanted to Know about CRC's	291	(1)
Supporting Verilog Modules	292	(1)
Appendix A: Tutorial Questions and Discussion	293	(16)
Structural Descriptions	293	(10)
Testbench Modules	303	(1)
Combinational Circuits Using always	303	(2)
Sequential Circuits	305	(3)
Hierarchical Descriptions	308	(1)
Appendix B: Lexical Conventions	309	(6)
White Space and Comments	309	(1)
Operators	310	(1)
Numbers	310	(1)
Strings	311	(1)
Identifiers, System Names, and Keywords	312	(3)
Appendix C: Verilog Operators	315	(8)
Table of Operators	315	(5)
Operator Precedence	320	(1)
Operator Truth Tables	321	(1)
Expression Bit Lengths	322	(1)
Appendix D: Verilog Gate Types	323	(6)
Logic Gates	323	(2)
BUF and NOT Gates	325	(1)
BUFIF and NOTIF Gates	326	(1)
MOS Gates	327	(1)
Bidirectional Gates	328	(1)
CMOS Gates	328	(1)
Pullup and Pulldown Gates	328	(1)
Appendix E: Registers, Memories, Integers, and Time	329	(4)
Registers	329	(1)
Memories	330	(1)
Integers and Times	331	(2)
Appendix F: System Tasks and Functions	333	(6)
Display and Write Tasks	333	(1)
Continuous Monitoring	334	(1)
Strobed Monitoring	335	(1)
File Output	335	(1)
Simulation Time	336	(1)
Stop and Finish	336	(1)
Random	336	(1)
Reading Data From Disk Files	337	(2)
Appendix G: Formal Syntax Definition	339	(34)
Tutorial Guide to Formal Syntax Specification	339	(4)
Source text	343	(3)
Declarations	346	(5)
Primitive instances	351	(2)
Module and generated instantiation	353	(2)
UDP declaration and instantiation	355	(1)
Behavioral statements	355	(4)
Specify section	359	(6)
Expressions	365	(5)
General	370	(3)
Index	373