The VHDL Reference A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS

by Heinkel, Ulrich; Padeffke, Martin; Haas, Werner; Buerner, Thomas; Braisz, Herbert; Gentner, Thomas; Grassmann, Alexander

• ISBN13: 9780471899723
• ISBN10: 0471899720
• Edition: 1st
• Format: Hardcover
• Copyright: 2000-06-08
• Publisher: WILEY

Summary

The VHDL Reference: The essential guide for students and professionals working in computer hardware design and synthesis. The definitive guide to VHDL, this book combines a comprehensive reference of the VHDL syntax with tutorial and workshop materials that guide the reader through the principles of digital hardware design. The Authors describe the concept of VHDL and VHDL-AMS for modelling and synthesis and explain how VHDL can be used for the design of digital systems. The CD-ROM features workshop and reference material to familiarise beginners with the use of VHDL for simulation and for synthesis. In-depth examples of VHDL construct are explained in compact and easy to follow form providing immediate help and answers to specific problems. Features include: * Accompanying CD-ROM version of the VHDL Reference including demonstration tools and workshop material covering language aspects for digital systems. * Modelling tutorial featuring VHDL-AMS, the new standard for modelling and simulating mixed signal micro systems. Real-life examples enable the reader to test their knowledge and clarify their understanding of the concepts. * Design workshop format taking the reader through an entire circuit design using an actual design problem, allowing beginners to put their VHDL skills into practice. * A user friendly reference section providing in depth coverage of the VHDL language for digital systems. * Includes tools for editing VHDL source files, simulating and synthesising VHDL models. The VHDL Reference is a highly accessible single source reference to the industry standard language for computer-aided electronic system design. It is not only an essential guide for undergraduate and postgraduate students in electrical engineering but also an indispensable aid to researchers and hardware designers and teachers using VHDL and logic synthesis.

Author Biography

Ulrich Heinkel is the author of The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design including VHDL-AMS, published by Wiley.

Table of Contents

Preface	xvii
VHDL TUTORIAL
VHDL: Overview and Application Field	3	(19)
Application Field of HDLs	3	(3)
Application of HDLs (1)	4	(1)
Application of HDLs (2)	5	(1)
Range of Use	6	(1)
VHDL: Overview	7	(4)
VHDL: History	8	(1)
VHDL: Application Field	9	(1)
ASIC Development	10	(1)
Concepts of VHDL	11	(10)
Abstraction	12	(1)
Abstraction Levels in IC Design	13	(1)
Abstraction Levels and VHDL	14	(1)
Description of Abstraction Levels	15	(1)
Behavioural Description in VHDL	16	(1)
RT Level in VHDL	17	(1)
Gate Level in VHDL	18	(1)
Information Content of Abstraction Levels	19	(1)
Modularity and Hierarchy	20	(1)
Summary	21	(1)
VHDL Language and Syntax	22	(82)
General	22	(3)
Identifier	23	(1)
Naming Convention	24	(1)
VHDL Structural Elements	25	(25)
Declaration of VHDL Objects	26	(1)
Entity	27	(1)
Architecture	28	(1)
Architecture Structure	29	(1)
Entity Port Modes	30	(1)
Hierarchical Model Layout	31	(1)
Component Declaration	32	(1)
Component Instantiation	33	(1)
Component Instantiation: Named Signal Association	34	(1)
Configuration	35	(1)
Configuration: Task and Application	36	(1)
Configuration: Example (1)	37	(1)
Configuration: Example (2)	38	(1)
Process	39	(1)
VHDL Communication Model	40	(1)
Signals	41	(1)
Package	42	(1)
Library	43	(1)
Design Structure: Example	44	(1)
Sequence of Compilation	45	(1)
Outlook: Testbench	46	(1)
Simple Testbench Example	47	(1)
Summary	48	(2)
Sequential Statements	50	(12)
IF Statement	50	(1)
IF Statement: Example	51	(1)
CASE Statement	52	(1)
CASE Statement: Example	52	(1)
Defining Ranges	53	(1)
FOR Loops	54	(1)
Loop Syntax	54	(1)
Loop Examples	55	(1)
WAIT Statement	56	(1)
WAIT Statement: Examples	56	(1)
WAIT Statements and Behavioural Modelling	57	(1)
Variables	58	(1)
Variables vs. Signals	58	(1)
Use of Variables	59	(1)
Variables: Example	60	(1)
Global Variables (VHDL'93)	60	(2)
Concurrent Statements	62	(4)
Conditional Signal Assignment	62	(1)
Conditional Signal Assignment: Example	63	(1)
Selected Signal Assignment	64	(1)
Selected Signal Assignment: Example	64	(1)
Concurrent Statements: Summary	65	(1)
Data Types	66	(8)
Standard Data Types	66	(1)
Data type `time'	67	(1)
Definition of Arrays	68	(1)
`integer' and `bit' Types	68	(1)
Assignments with Array Types	69	(1)
Bit String Literals	70	(1)
Concatenation	71	(1)
Aggregates	72	(1)
Slices of Arrays	73	(1)
Extended Data Types	74	(16)
Type Classification	75	(1)
Enumeration Types	76	(1)
Enumeration Types: Example	77	(1)
BIT Type Issues	78	(1)
Multivalued Types	78	(1)
IEEE Standard Logic Type	79	(1)
Resolved and Unresolved Types	80	(1)
Std_Logic vs. 1164 Package	80	(1)
Resolution Function	81	(1)
STD_LOGIC vs. STD_ULOGIC	82	(1)
The NUMERIC_STD Package	83	(1)
Arrays	84	(1)
Multidimensional Arrays	84	(1)
Aggregates and Multidimensional Arrays	85	(1)
Records	86	(1)
Type Conversion	87	(1)
Subtypes	88	(1)
Aliases	88	(2)
Operators	90	(4)
Logical Operators	90	(1)
Logical Operations with Arrays	91	(1)
Shift Operators: Examples	91	(1)
Relational Operators	92	(1)
Comparison Operations with Arrays	92	(1)
Arithmetic Operators	93	(1)
Subprograms	94	(5)
Parameters and Modes	95	(1)
Functions	96	(1)
Procedures	97	(2)
Subprogram Declaratio and Overloading	99	(5)
Overloading Example	100	(1)
Overloading: Illegal Redeclarations	100	(1)
Overloading: Ambiguity	101	(1)
Operator Overloading	102	(1)
Operator Overloading: Example	102	(2)
Synthesis	104	(50)
What is Synthesis?	104	(6)
Synthesizability	104	(1)
Different Language Support for Synthesis	105	(1)
How to Do?	106	(1)
Essential Information for Synthesis	106	(1)
Synthesis Process in Practice	107	(1)
Problems with Synthesis Tools	108	(1)
Synthesis Strategy	109	(1)
RTL Style	110	(8)
Combinational Process: Sensitivity List	111	(1)
WAIT Statement <-> Sensitivity List	112	(1)
Combinational Process: Incomplete Assignments	113	(1)
Clocked Process: Clock Edge Detection	114	(1)
Register Inference	115	(1)
Asynchronous Set/Reset	116	(1)
Summary: Combinational Process (Rules)	117	(1)
Summary: Clocked Process (Rules)	117	(1)
Combinational Logic	118	(10)
Feedback Loops	118	(1)
Coding Style Influence	118	(1)
Source Code Optimization	119	(1)
Example of a Multiplier	120	(4)
Synthesis of Operators	124	(1)
IF Structure <-> CASE Structure	125	(1)
Implementation of a Data Bus	126	(2)
Sequential Logic	128	(2)
Initialization	128	(1)
RTL: Combinational Logic and Registers	128	(1)
Variables in Clocked Processes	129	(1)
Finite State Machine and VHDL	130	(19)
One `State' Process	131	(1)
Two `State' Processes	132	(1)
How Many Processes?	133	(1)
State Encoding	134	(1)
Extension of CASE Statement	135	(1)
Extension of Type Declaration	136	(1)
Hand Coding	137	(1)
FSM: Medvedev	138	(1)
Medvedev Example	138	(1)
`Waveform Medvedev Example	139	(1)
FSM: Moore	140	(1)
Moore Example	140	(1)
Waveform Moore Example	141	(1)
FSM: Mealy	142	(1)
Mealy Example	142	(1)
Waveform Mealy Example	143	(1)
Modelling Aspects	144	(1)
Registered Output	145	(1)
Registered Output Example (1)	146	(1)
Waveform Registered Output Example (1)	146	(1)
Registered Output Example (2)	147	(1)
Waveform Registered Output Example (2)	148	(1)
Advanced Synthesis	149	(5)
Parameterization via Constants	150	(1)
Parameterization via Generics (1)	150	(1)
Parameterization via Generics (2)	151	(1)
GENERATE Statement	152	(1)
Conditional GENERATE Statement	152	(1)
`Parameterization' via Signals	153	(1)
Simulation	154	(30)
Testbenches	154	(5)
Structure of a VHDL Testbench	155	(1)
Example	156	(3)
Sequence of Compilation	159	(2)
File I/O	161	(6)
Example for File I/O (1/4)	162	(4)
File Declaration: VHDL'87 versus VHDL'93	166	(1)
Simulation Flow	167	(3)
Elaboration	167	(1)
Initialization	168	(1)
Execution	168	(2)
Process Execution	170	(6)
Concurrent vs. Sequential Execution	170	(1)
Signal Update	171	(1)
Delta Cycles (1)	172	(1)
Delta Cycles (2)	172	(1)
Delta Cycles: Example	173	(1)
Process Behaviour	174	(1)
Postponed Processes	174	(2)
Delay Models	176	(8)
Projected Output Waveforms (LRM)	177	(1)
Transport Delay (1)	178	(1)
Transport Delay (2)	179	(1)
Inertial Delay (1)	180	(1)
Inertial Delay (2)	181	(1)
Inertial Delay (3)	182	(2)
Project Management	184	(13)
File Organization	184	(1)
Design Components	184	(3)
Libraries	185	(1)
The LIBRARY Statement	186	(1)
The USE Statement	186	(1)
Name Spaces	187	(3)
Packages	188	(1)
Package Syntax	188	(1)
Package Example	189	(1)
Design Reuse	190	(7)
Why Reuse?	190	(1)
Design for Reuse	191	(1)
Bad Example	192	(1)
Good Example (1/2)	192	(1)
Good Example (2/2)	193	(4)
VHDL-AMS TUTORIAL
VHDL-AMS	197	(36)
Overview and Introduction	197	(9)
Current Design Flow	198	(1)
IC Design with VHDL-AMS	199	(1)
Application Fields in System Design	200	(1)
Discrete System--Continuous System (1)	201	(1)
Discrete System--Continuous System (2)	201	(1)
Discrete System--Continuous System (3)	202	(1)
Simulation Cycle (1)	203	(1)
Simulation Cycle (2)	204	(1)
Analogue--Digital Coupling	205	(1)
New VHDL-AMS Language Elements	206	(20)
Natures	207	(1)
Types of Natures	208	(1)
Terminals	209	(1)
Quantities	210	(1)
Branch Quantity	211	(1)
Interface Quantity	212	(1)
Tolerance	213	(1)
Frequency and Noise	214	(1)
Analogue--Digital Interface	215	(1)
Attributes for Natures and Terminals	216	(1)
Attributes for Terminals	217	(1)
Attributes for Quantities	218	(1)
Attributes for Signals	219	(1)
Example: Simple Diode Model	220	(1)
Concurrent Break Statement	221	(1)
Sequential Break Statement	222	(1)
Simultaneous Statements	223	(1)
Simultaneous Procedural Statement	224	(1)
Simultaneous If/Case Statement	225	(1)
Modelling	226	(7)
Analogue Modelling Modes	226	(1)
Networks	227	(1)
VHDL-AMS vs. SPICE	228	(1)
DAEs	229	(1)
Signal Flows	230	(3)
VHDL WORKSHOP
Introduction	233	(2)
Structure of the Exercises	233	(1)
Style Guide	233	(1)
Design Structure	233	(2)
VHDL Working Environment	235	(6)
Directory Structure	235	(1)
Working Environment	235	(1)
VHDL Code	236	(1)
VHDL Complier	237	(1)
VHDL Simulator	237	(2)
VHDL Synthesis	239	(2)
Exercises	241	(28)
A Multiplexer	241	(2)
Extending the Multiplexer	243	(2)
A 7-Segment Display Driver	245	(3)
A Three Digit 7-Segment Display Driver	248	(1)
A Decoder	249	(3)
A Register	252	(2)
A State Machine for the Display	254	(2)
A Timer	256	(2)
A BCD Counter	258	(4)
A State Machine for the Main Controller	262	(2)
The Camera	264	(5)
REFERENCE
Design Entities and Configurations	269	(5)
Entity	269	(1)
Architecture	270	(2)
Configuration	272	(2)
Subprograms and Packages	274	(10)
Subprogram Declaration	274	(1)
Subprogram Body	275	(2)
Overloading	277	(2)
Resolution Function	279	(1)
Package Declaration	280	(1)
Package Body	281	(2)
Conformance Rules	283	(1)
Types	284	(4)
Scalar Types	284	(1)
Compound Types	285	(1)
Access Types	286	(1)
File Types	287	(1)
Declarations	288	(18)
Type Declarations	288	(1)
Subtype Declarations	289	(2)
Constant Declarations	291	(1)
Signal Declarations	292	(2)
Variable Declarations	294	(2)
File Declarations	296	(2)
Interface Declarations	298	(1)
Alias Declarations	298	(3)
Attribute Declarations	301	(1)
Component Declarations	302	(1)
Group Template Declarations	303	(1)
Group Declaration	304	(2)
Specification	306	(5)
Attribute Specification	306	(1)
Configuration Specification	307	(2)
Disconnection Specification	309	(2)
Names	311	(3)
Name	311	(1)
Simple Names	311	(1)
Selected Names	311	(1)
Indexed Names	312	(1)
Range Names	312	(1)
Attribute Names	313	(1)
Expressions	314	(11)
Expression	314	(1)
Logic Operators	314	(1)
Relational Operators	315	(1)
Shift Operators	316	(1)
Adding Operators	317	(1)
Multiplying Operators	318	(1)
Miscellaneous Operators	319	(1)
Literals	320	(1)
Aggregates	320	(1)
Function Call	321	(1)
Qualified Expression	321	(1)
Type Conversion	322	(1)
Allocator	322	(1)
Static Expression	323	(1)
Universal Expression	324	(1)
Sequential Statements	325	(18)
Wait	325	(1)
Assertion	326	(2)
Report	328	(1)
Signal Assignment	329	(2)
Variable Assignment	331	(1)
Procedure Call	332	(1)
IF	333	(2)
Case	335	(1)
Loop	336	(2)
Next	338	(1)
Exit	339	(2)
Return	341	(1)
Null	342	(1)
Concurrent statements	343	(15)
Block	343	(1)
Process	344	(2)
Concurrent Procedure Call	346	(2)
Concurrent Assertion	348	(1)
Concurrent Signal Assignment	349	(3)
Component Instantiation	352	(3)
Generate Statement	355	(3)
Miscellaneous	358	(5)
Visibility and Validity Ranges	358	(3)
Use Statements	361	(1)
Design Units and Their Analysis	362	(1)
Elaboration and Simulation	363	(16)
Elaboration of a Blockheader	363	(2)
Elaboration of a Declaration	365	(5)
Elaboration of a Statement Part	370	(3)
Dynamic Elaboration	373	(1)
Elaboration of a Design Hierarchy	374	(1)
Execution of a Model	375	(4)
Lexical Elements	379	(5)
Character Set	379	(1)
Delimiters	379	(1)
Identifiers	380	(1)
Abstract Literals	380	(1)
Character Literals	381	(1)
String Literals	381	(1)
Bit String Literals	382	(1)
Comments	382	(1)
Reserved Words	383	(1)
Replacing Characters	383	(1)
Predefined Attributes	384	(9)
Package Standard	393	(2)
Package Textio	395	(2)
BNF	397	(16)
Literature	413	(2)
Index	415