VLSI Design for Video Coding

by Lin, Youn-Long Steve; Kao, Chao-yang; Kuo, Huang-Chih; Chen, Jian-wen

• ISBN13: 9781441909589
• ISBN10: 1441909583
• Format: Hardcover
• Copyright: 2010-01-30
• Publisher: Springer Verlag

Summary

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing. This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.

Table of Contents

Introduction to Video Coding and H.264/AVC	p. 1
Introduction	p. 1
Basic Coding Unit	p. 2
Video Encoding Flow	p. 2
Color Space Conversion	p. 2
Prediction of a Macroblock	p. 3
Intraframe Prediction	p. 4
Interframe Prediction	p. 4
Motion Vector	p. 4
Prediction Error	p. 4
Space-Domain to Frequency-Domain Transformation of Residual Error	p. 5
Coefficient Quantization	p. 5
Reconstruction	p. 5
Motion Compensation	p. 5
Deblocking Filtering	p. 6
Book Organization	p. 6
Intra Prediction	p. 11
Introduction	p. 11
Algorithm	p. 12
Design Consideration	p. 16
Related Works	p. 19
Prediction Time Reduction Approaches	p. 19
Hardware Area Reduction Approaches	p. 19
A VLSI Design for Intra Prediction	p. 20
Subtasks Scheduling	p. 20
Architecture	p. 24
Evaluation	p. 30
Summary	p. 30
Integer Motion Estimation	p. 31
Introduction	p. 31
Algorithms	p. 33
Design Considerations	p. 36
Related Works	p. 37
Architecture	p. 37
Data-Reuse Schemes	p. 43
A VLSI Design for Integer Motion Estimation	p. 44
Proposed Data-Reuse Scheme	p. 45
Architecture	p. 47
Data Flow	p. 49
Evaluation	p. 52
Summary	p. 53
Fractional Motion Estimation	p. 57
Introduction	p. 57
Algorithms	p. 58
Design Considerations	p. 61
Related Works	p. 61
A VLSI Design for Fractional Motion Estimation	p. 63
Proposed Architecture	p. 63
Proposed Resource Sharing Method for SATD Generator	p. 68
Evaluation	p. 72
Summary	p. 72
Motion Compensation	p. 73
Introduction	p. 73
Algorithms	p. 73
Design Considerations	p. 75
Related Works	p. 75
Memory Traffic Reduction	p. 76
Interpolation Engine	p. 76
A VLSI Design for Motion Compensation	p. 77
Motion Vector Generator	p. 77
Interpolator	p. 79
Evaluation	p. 83
Summary	p. 83
Transform Coding	p. 85
Introduction	p. 85
Algorithms	p. 85
Design Consideration	p. 97
Related Works	p. 97
Multitransform Engine Approaches	p. 97
Trans/Quan or InvQuan/InvTrans Integration Approaches	p. 97
A VLSI Design for Transform Coding	p. 98
Subtasks Scheduling	p. 98
Architecture	p. 98
Evaluation	p. 106
Summary	p. 106
Deblocking Filter	p. 107
Introduction	p. 107
Deblocking Filter Algorithm	p. 108
Subtasks Processing Order	p. 112
Design Considerations	p. 113
Related Works	p. 115
A VLSI Design for Deblocking Filter	p. 116
Subtasks Scheduling	p. 116
Architecture	p. 116
Evaluation	p. 122
Summary	p. 124
CABAC Encoder	p. 125
Introduction	p. 125
CABAC Encoder Algorithm	p. 125
Subtasks Processing Order	p. 134
Design Consideration	p. 134
Related Works	p. 136
A VLSI Design for CABAC Encoder	p. 139
Subtasks Scheduling	p. 139
Architecture	p. 140
Evaluation	p. 147
Summary	p. 148
System Integration	p. 151
Introduction	p. 151
Algorithm	p. 151
Design Consideration	p. 153
Related Works	p. 155
A VLSI Design for H.264/AVC Encoder	p. 156
Subtasks Scheduling	p. 156
Architecture	p. 159
Evaluation	p. 165
Summary	p. 166
References	p. 167
Index	p. 173
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