A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole | p. 1 |
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks | p. 22 |
Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption | p. 43 |
A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4 | p. 69 |
Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE | p. 100 |
VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MTMO Systems | p. 128 |
Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression | p. 155 |
Fast Fixed-Point Optimization of DSP Algorithms | p. 182 |
Design and Verification of Lazy and Hybrid Implementations of theSELF Protocol | p. 206 |
Adaptation Strategies in Multiprocessors System on Chip | p. 233 |
Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits | p. 258 |
Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization | p. 291 |
Control Electronics Integration toward Endoscopic Capsule Robot Performing Legged Locomotion and Illumination | p. 312 |
Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems | p. 339 |
Author Index | p. 355 |
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