Vlsi-soc from Systems to Silicon: Proceedings of Ifip Tc 10/ Wg 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip Vlsi-soc 2005, October 17-19,

by Reis, Ricardo

• ISBN13: 9780387736600
• ISBN10: 0387736603
• Edition: 1st
• Format: Hardcover
• Copyright: 2007-08-01
• Publisher: SPRINGER

Summary

This book contains extended and revised versions of the best papers that were presented during the thirteenth edition of the IFIP TC 10 International Conference on Very Large Scale Integration, a Global System-on-Chip Design and CAD conference. This conference provides a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design.

Table of Contents

Molecular Electronics - Devices and Circuits Technology	p. 1
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgement Signals	p. 11
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures	p. 25
Defragmentation Algorithms for Partially Reconfigurable Hardware	p. 41
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits	p. 55
3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System	p. 71
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms	p. 87
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault-Tolerance Analysis	p. 111
Issues in Model Reduction of Power Grids	p. 127
A Traffic Injection Methodology with Support for System-Level Synchronization	p. 145
Pareto Points in SRAM Design Using the Sleepy Stack Approach	p. 163
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs	p. 179
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping	p. 195
A Novel MicroPhotonic Structure for Optical Header Recognition	p. 209
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint	p. 221
On-chip Pseudorandom Testing for Linear and Nonlinear MEMS	p. 245
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles	p. 267
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction	p. 283
Exact BDD Minimization for Path-Related Objective Functions	p. 299
Current Mask Generation: an Analog Circuit to Thwart DPA Attacks	p. 317
A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming	p. 331
Table of Contents provided by Blackwell. All Rights Reserved.