9780769503875

XII Symposium on Integrated Circuits and Systems Design: Proceedings Natal-Rn, Brazil September 29-October 2, 1999

by ; ; ; ; ; ;
  • ISBN13:

    9780769503875

  • ISBN10:

    076950387X

  • Format: Paperback
  • Copyright: 1999-06-01
  • Publisher: IEEE
  • Purchase Benefits
List Price: $115.00
We're Sorry.
No Options Available at This Time.

Table of Contents

Foreword xi
Symposium Committees x
Reviewers xii
Sponsoring Societies xiii
Tutorial 1
Jose Monteiro da Mata
Microprocessors for the Years 2001 and 2008: Where Will We be in 2001? What Will Still Need to be Done for 2008?
2(2)
Y. Patt
Session 1: Microprocessors Design
Eliseu Monteiro Chaves Filho
Jose Monteiro de Mata
Micro-Architecture Estimation of the Useless Power Consumption of a High-Performance Processor
4(4)
E. Musoll
A Bit Scalable Architecture for Fuzzy Processors
8(4)
R. d'Amore
K. Kienitz
O. Saotome
Designing a JAVA Microcontroller to Specific Applications
12(6)
S. Ito
L. Carro
R. Jacobi
Session 2: Modelling
Jacobus Swart
Mario Vaz da Silva Filho
Advanced Compact Model for the Charges and Capacitances of Short-Channel MOS Transistors
18(4)
O. Gouveia-Filho
M. Schneider
C. Galup-Montoro
Conductances and Noise in Trapezoidal Association of Transistors for Analog Applications Using a SOT Methodology
22(4)
J. Choi
S. Bampi
Multilevel Finite Difference Methods for the Characterization of Substrate Coupling in Deep Sub-Micron Designs
26(6)
L. Silveira
N. Vargas
Session 3: Co-Design
Carlos A. Valderrama
Estimating Functional Unit Number in the PISH Codesign System by using Petri Nets
32(4)
P. Maciel
E. Barros
W. Rosenstiel
Codesign System Performance based on Memory Configurations
36(6)
L. Mourelle
N. Nedjah
Hardware/Software Specification, Design and Test using a System Level Approach
42(4)
O. Dias
J. Semiao
C. Pereira
I. Teixeira
J. Teixeira
An Approach for Microsystems Codesign
46(6)
R. Ribas
F. Behrens
Session 4: Analog Design
Oscar Calvo
Antonio Petraglia
A Multi-Functional Cell for CMOS Analog Applications in Low-Voltage
52(4)
C. Lin
T. Pimenta
M. Ismail
L. Caldeira
Optimum Design of MOS Amplifiers
56(4)
R. Pinto
M. Schneider
C. Galup-Montoro
Odd-Order Current-Mode Lowpass Filters with Finite Zeros
60(6)
F. Galvez-Durand
Session 5: High Level Synthesis
Luigi Carro
An Approach for Interface Generation in the PISH Co-Design System
66(4)
C. Araujo
E. Barros
Interface Design and Refinement using State based Techniques
70(4)
H. Klapuri
J. Takala
J. Saarinen
Register Files Constraint Satisfaction during Scheduling of DSP code
74(4)
C. Pinto
B. Mesman
K. van Eijk
A Binary-Tree Architecture for Scheduling Real-Time Systems with Hard and Soft Tasks
78(6)
A. Garcia
J. Vila
A. Crespo
S. Saez
Session 6: Digital Design I
Julio Salek
Ivan Chueiri
An 0.25μm CMOS Injection Locked 5.6Gb/s Clock and Data Recovery Cell
84(4)
T. Gabara
An 9-Bit Parallel Pipelined Multiplier based on the 3-bit Recoding from Booth's Algorithm
88(4)
L. Caldeira
T. Pimenta
E. Cotrim
MCA: A Single Chip One-Port Scalable ATM Layer Controller
92(6)
J. de Lima
E. Melchier
A. Cavalcanti
Tutorial 2
Flavio Wagner
David Deharbe
Symbolic Model Checking in Practice
98(8)
S. Campos
Panel: Is Open Source CAD Software the Way for Innovation?
Meryem Marzouki
Panel Statement
104(2)
Session 7: Mixed-Signal Design and Test, IEEE TTTC-LA Special Session
Franco Maloberti
Federico Galvez-Durand
Circuit-Level Considerations for Mixed Signals Programmable Components
106(4)
L. Carro
Fault Detection in Systems with 2nd Order Dynamics using Transient Analysis
110(5)
J. Calvano
V. Alves
M. Lubaszewski
A Low Sensitivity Switched-Capacitor Filter Design with Testability Features
115(5)
J. Canive
J. Gomes
A. Petraglia
Session 8: Digital Design II
Antonio Ferrari
Manoel Lois
Reusing Hardware Components with Single-State Processes
120(4)
A. de melo
High Speed FIR Filters for Digital Decimation
124(4)
M. Brambilla
D. Guidi
V. Liberali
An FPGA Version of a Non-Linear Adaptive Filter
128(6)
D. Franco
L. Carro
Tutorial 3
Michel Robert
Ricardo Reis
Power Optimization using Dynamic Power Management
134(8)
J. Monteiro
Session 9: Synthesis and Reconfiguration
Manfred Glesner
Ricardo Jacobi
Logic and High Level Synthesis for Communication Protocols
142(4)
R. Lima
E. Carli
A. Pedroza
L. Pirmez
A. de Mesquita
System Synthesis and Processor Selection in the S3E2S Environment
146(4)
L. Carro
M. Kreutz
F. Wagner
M. Oyamada
Fast Hardware Compilation of Behaviors into an FPGA-based Dynamic Reconfigurable Computing Systems
150(4)
J. Cardoso
H. Neto
An Architect's Workbench for Reconfigurable Computing
154(6)
I. Skliarova
A. Ferrari
Session 10: Digital Testing I, IEEE TTTC-LA Special Session
Vitor Champac
Vladimir Castro Alves
Test Escapes: Analysis of Short Defect
160(4)
M. Renovell
F. Azais
Y. Bertrand
Effects of Radiation on Digital Architectures: One Year Results from a Satellite Experiment
164(6)
R. Velazco.
P. Cheynet
R. Ecoffet
Criteria for Static Current Estimation: How Good are They? An Approach Incorporating IC Quality Requirements
170(4)
F. Vargas
M. Nicolaidis
On-Line Testing of a Switching Circuit
174(6)
J. Bastos
J. Kussler
L. Cassol
M. Lubaszewski
Session 11: CAD Tools
Manoel Eusebio
Covering Strategies for Library Free Technology Mapping
180(4)
A. Reis
A Tool for Analysis of Universal Logic Gates Functionality
184(4)
F. de Lima
M. Johann
J. Guntzel
L. Carro
R. Reis
Project Management and Design Methodology Support for the CAVE Project: A Hyperdocument-Centric Approach
188(4)
L. Indrusiak
R. Reis
Solving Satisfiability in Combinational Circuits with Bactrack Search and Recursive Learning
192(6)
J. Marques-Silva
L. Silva
Session 12: Digital Testing II, IEEE TTTC-LA Special Session
Marcel Jacomet
Fabian Vargas
Comparison between Quasi-Uniform Linear Cellular Automata and Linear Feedback Shift Registers as Test Pattern Generators for Built-in Self-Test Applications
198(4)
P. Cardoso
M. Strum
J. Amazonas
W. Chau
Implementing a Self-Testing 8051 Microprocessor
202(4)
E. Cota
M. Krug
M. Lubaszewski
L. Carro
A. Susin
Design for Testability Reuse in Synthesis for Testability
206(6)
P. Bukovjan
M. Marzouki
W. Maroufi
Session 13: IP Cores
Altamiro Susin
Yervant Zorian
Semiconductor Knowledge Management and Soft-Cores Reuse
212(4)
S. Olcoz
Specification and Design of an Ethernet Interface Soft IP
216(4)
J. Fragoso
E. Costa
J. Rochol
S. Bampi
R. Reis
SCOB, A Soft-Core for the Blowfish Cryptographic Algorithm
220(6)
S. Salomao
J. de Alcantara
V. Alves
A. Vieira
Tutorial 4
Antonio Otavio Fernandes
Marcelo Lubaszewski
Testing Semiconductor Chips: Trends and Solutions
226(9)
Y. Zorian
Index of Authors 235

Rewards Program

Reviews for XII Symposium on Integrated Circuits and Systems Design: Proceedings Natal-Rn, Brazil September 29-October 2, 1999 (9780769503875)