What is included with this book?
Invited Program | |
Embedded Systems as Datacenters (Keynote) | p. 1 |
Larrabee: A Many-Core Intel Architecture for Visual Computing (Keynote) | p. 2 |
Architectural Support for Concurrency | |
Remote Store Programming: A Memory Model for Embedded Multicore | p. 3 |
Low-Overhead, High-Speed Multi-core Barrier Synchronization | p. 18 |
Improving Performance by Reducing Aborts in Hardware Transactional Memory | p. 35 |
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems | p. 50 |
Compilation and Runtime Systems | |
Split Register Allocation: Linear Complexity Without the Performance Penalty | p. 66 |
Trace-Based Data Layout Optimizations for Multi-core Processors | p. 81 |
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors | p. 96 |
Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures | p. 111 |
Reconfigurable and Customized Architectures | |
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions | p. 126 |
Accelerating XML Query Matching through Custom Stack Generation on FPGAs | p. 141 |
An Application-Aware Load Balancing Strategy for Network Processors | p. 156 |
Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays | p. 171 |
Multicore Efficiency, Reliability, and Power | |
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors | p. 186 |
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors | p. 201 |
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor | p. 216 |
Performance and Power Aware CMP Thread Allocation Modeling | p. 232 |
Memory Organization and Optimization | |
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching | p. 247 |
Scalable Shared-Cache Management by Containing Thrashing Workloads | p. 262 |
SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs | p. 277 |
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems | p. 292 |
Programming and Analysis of Accelerators | |
Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor | p. 307 |
Analysis of Task Offloading for Accelerators | p. 322 |
Offload – Automating Code Migration to Heterogeneous Multicore Systems | p. 337 |
Computer Generation of Efficient Software Viterbi Decoders | p. 353 |
Author Index | p. 369 |
Table of Contents provided by Ingram. All Rights Reserved. |
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