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9783642115141

High Performance Embedded Architectures and Compilers : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings

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  • ISBN13:

    9783642115141

  • ISBN10:

    3642115144

  • Edition: 1st
  • Format: Paperback
  • Copyright: 2010-03-06
  • Publisher: Springer-Verlag New York Inc
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Supplemental Materials

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Summary

This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010.The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators.

Table of Contents

Invited Program
Embedded Systems as Datacenters (Keynote)p. 1
Larrabee: A Many-Core Intel Architecture for Visual Computing (Keynote)p. 2
Architectural Support for Concurrency
Remote Store Programming: A Memory Model for Embedded Multicorep. 3
Low-Overhead, High-Speed Multi-core Barrier Synchronizationp. 18
Improving Performance by Reducing Aborts in Hardware Transactional Memoryp. 35
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systemsp. 50
Compilation and Runtime Systems
Split Register Allocation: Linear Complexity Without the Performance Penaltyp. 66
Trace-Based Data Layout Optimizations for Multi-core Processorsp. 81
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessorsp. 96
Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architecturesp. 111
Reconfigurable and Customized Architectures
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensionsp. 126
Accelerating XML Query Matching through Custom Stack Generation on FPGAsp. 141
An Application-Aware Load Balancing Strategy for Network Processorsp. 156
Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arraysp. 171
Multicore Efficiency, Reliability, and Power
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessorsp. 186
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessorsp. 201
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processorp. 216
Performance and Power Aware CMP Thread Allocation Modelingp. 232
Memory Organization and Optimization
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matchingp. 247
Scalable Shared-Cache Management by Containing Thrashing Workloadsp. 262
SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPsp. 277
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systemsp. 292
Programming and Analysis of Accelerators
Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processorp. 307
Analysis of Task Offloading for Acceleratorsp. 322
Offload – Automating Code Migration to Heterogeneous Multicore Systemsp. 337
Computer Generation of Efficient Software Viterbi Decodersp. 353
Author Indexp. 369
Table of Contents provided by Ingram. All Rights Reserved.

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