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| Revisiting graph coloring register allocation : a study of the Chaitin-Briggs and Callahan-Koblenz algorithms | p. 1 |
| Register pressure in software-pipelined loop nests : fast computation and impact on architecture design | p. 17 |
| Manipulating MAXLIVE for spill-free register allocation | p. 32 |
| Optimizing packet accesses for a domain specific language on network processors | p. 47 |
| Array replication to increase parallelism in applications mapped to configurable architectures | p. 62 |
| Generation of control and data flow graphs from scheduled and pipelined assembly code | p. 76 |
| Applying data copy to improve memory performance of general array computations | p. 91 |
| A cache-conscious profitability model for empirical tuning of loop fusion | p. 106 |
| Optimizing matrix multiplication with a classifier learning system | p. 121 |
| A language for the compact representation of multiple program versions | p. 136 |
| Efficient computation of may-happen-in-parallel information for concurrent Java programs | p. 152 |
| Evaluating the impact of thread escape analysis on a memory consistency model-aware compiler | p. 170 |
| Concurrency analysis for parallel programs with textually aligned barriers | p. 185 |
| Titanium performance and potential : an NPB experimental study | p. 200 |
| Efficient search-space pruning for integrated fusion and tiling transformations | p. 215 |
| Automatic measurement of instruction cache capacity | p. 230 |
| Combined ILP and register tiling : analytical model and optimization framework | p. 244 |
| Analytic models and empirical search : a hybrid approach to code optimization | p. 259 |
| Testing speculative work in a lazy/eager parallel functional language | p. 274 |
| Loop selection for thread-level speculation | p. 289 |
| Software thread level speculation for the Java language and virtual machine environment | p. 304 |
| Lightweight monitoring of the progress of remotely executing computations | p. 319 |
| Using platform-specific performance counters for dynamic compilation | p. 334 |
| A domain-specific interpreter for parallelizing a large mixed-language visualisation application | p. 347 |
| Compiler control power saving scheme for multi core processors | p. 362 |
| Code transformations for one-pass analysis | p. 377 |
| Scalable array SSA and array data flow analysis | p. 397 |
| Interprocedural symbolic range propagation for optimizing compilers | p. 413 |
| Parallelization of utility programs based on behavior phase analysis | p. 425 |
| A systematic approach to model-guided empirical search for memory hierarchy optimization | p. 433 |
| An efficient approach for self-scheduling parallel loops on multiprogrammed parallel computers | p. 441 |
| Dynamic compilation for reducing energy consumption of I/O-intensive applications | p. 450 |
| Supporting SELL for high-performance computing | p. 458 |
| Compiler supports and optimizations for PAC VLIW DSP processors | p. 466 |
| Table of Contents provided by Blackwell. All Rights Reserved. |
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