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An emerging technology or devices architecture called 3D IC integration is based on the system performance gains that can be achieved by stacking and vartically interconnecting distinct device chips The 3D concept of replacing long 2D interconnects with shorter vertical (3D) interconnect has the potential to alleviate the well-known interconnect.

Recent advances in 3-D integration at IMEC	p. 3
High density direct bond interconnect (DBI) technology for three-dimensional integrated circuit applications	p. 13
3-D integration latest developments at LETI	p. 25
Current and future three-dimensional LSI integration technology by "chip on chip," "chip on wafer," and "wafer on wafer"	p. 35
Exploration of the scaling limits of 3-D integration	p. 49
Modeling and simulation of parasitic effects in stacked silicon	p. 61
Thermo-mechanical reliability of 3-D-integrated microstructures in stacked silicon	p. 67
Current status of LSI micro-fabrication and future prospect for 3-D system integration	p. 79
Design and fabrication of 3-D microprocessors	p. 91
Three-dimensional integration of silicon chips for automotive applications	p. 103
3-D integration technology for high performance detector arrays	p. 115
Silicon through-hole interconnection for 3-D SiP using room temperature bonding	p. 125
Active Si interposer : combination of through-Si vias and redistribution	p. 133
CMOS-compatible through silicon vias for 3-D process integration	p. 145
Development of 3-D packaging process technology for stacked memory chips	p. 155
Through wafer interconnects for 3-D packaging	p. 163
Fabrication and evaluation of 3-D packages with through hole via	p. 171
Multi-stacked flip chips with copper plated through silicon vias and re-distribution for 3-D system-in-package integration	p. 179
Silicon layer stacking enabled by wafer bonding	p. 193
Damascene-patterned metal-adhesive (Cu-BCB) redistribution layers	p. 205
Vertical integration : a confederacy of alignment, bonding, and materials technologies	p. 215
Low temperature copper-nanorod bonding for 3-D integration	p. 225
3-D process integration - wafer-to-wafer and chip-to-wafer bonding	p. 231
High-performance temporary adhesives for wafer bonding applications	p. 239
Through-silicon-via copper deposition for vertical chip integration	p. 253
Materials aspects to consider in the fabrication of through-silicon vias	p. 261
Grinding and mixed silicon copper CMP of stacked patterned wafers for 3-D integration	p. 275
Novel wafer dicing and chip thinning technologies realizing high chip strength	p. 281
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Enabling Technologies for 3-d Integration

9781558999275

1558999272

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