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9780387243146

Matching Properties Of Deep Sub-micron Mos Transistors

by ; ;
  • ISBN13:

    9780387243146

  • ISBN10:

    0387243143

  • Format: Hardcover
  • Copyright: 2005-05-15
  • Publisher: Springer Verlag
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Summary

Matching Properties of Deep Sub-Micron MOS Transistors examines this interesting phenomenon. Microscopic fluctuations cause stochastic parameter fluctuations that affect the accuracy of the MOSFET. For analog circuits this determines the trade-off between speed, power, accuracy and yield. Furthermore, due to the down-scaling of device dimensions, transistor mismatch has an increasing impact on digital circuits. The matching properties of MOSFETs are studied at several levels of abstraction: A simple and physics-based model is presented that accurately describes the mismatch in the drain current. The model is illustrated by dimensioning the unit current cell of a current-steering D/A converter. The most commonly used methods to extract the matching properties of a technology are bench-marked with respect to model accuracy, measurement accuracy and speed, and physical contents of the extracted parameters. The physical origins of microscopic fluctuations and how they affect MOSFET operation are investigated. This leads to a refinement of the generally applied 1/area law. In addition, the analysis of simple transistor models highlights the physical mechanisms that dominate the fluctuations in the drain current and transconductance. The impact of process parameters on the matching properties is discussed. The impact of gate line-edge roughness is investigated, which is considered to be one of the roadblocks to the further down-scaling of the MOS transistor. Matching Properties of Deep Sub-Micron MOS Transistors is aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET.

Table of Contents

Preface ix
Acknowledgments xi
Introduction
1(12)
Matching analysis
2(2)
Importance for circuit design
4(2)
State of the art
6(2)
Research objectives
8(1)
Outline of this book
8(5)
Measurement and Modeling of Mismatch
13(34)
Measurement setup
14(6)
Measurement system
14(2)
Test structures
16(3)
Measurement algorithm
19(1)
Experimental setup
20(1)
Modeling of mismatch in the drain current
21(14)
Modeling approach
22(1)
Impact of threshold voltage mismatch
23(5)
Impact of current factor mismatch
28(2)
The complete model
30(1)
Parameter extraction
31(4)
Model accuracy
35(1)
Width and length dependence
35(6)
Width and length dependence of σ2ΔP
35(2)
Width and length dependence of correlation factors
37(1)
Matching properties of a 0.18 μm CMOS process
38(3)
Example: Yield of a current-steering D/A converter
41(4)
Accuracy of unit current cell based on a yield requirement
42(1)
Width and length of the unit current cell
42(3)
Conclusions
45(2)
Parameter Extraction
47(26)
Extraction methods
48(3)
Experimental setup
51(1)
Comparison of extraction methods
52(16)
Model accuracy
53(2)
Measurement accuracy and speed
55(6)
Physical meaningfulness of parameters
61(7)
Summary
68(1)
Future issues
68(2)
Conclusions
70(3)
Physical Origins of Mosfet Mismatch
73(56)
Basic operation of the MOS transistor
74(14)
Regions of operation and current expressions
74(6)
Short- and narrow-channel effects
80(5)
Gate depletion
85(1)
Quantummechanical effects
85(1)
Low field mobility
86(2)
Mismatch in the drain current
88(19)
Solution of the current equation in weak inversion
89(5)
Solution of the current equation in strong inversion
94(4)
Short- and narrow-channel effects
98(3)
Comparison of mismatch in weak and strong inversion
101(4)
Asymmetry of MOSFET mismatch
105(2)
Physical origins of fluctuations
107(19)
Doping fluctuations
108(1)
Impact of fluctuations in channel doping on threshold voltage
109(5)
Gate depletion
114(1)
Quantummechanical effects
115(3)
Mobility fluctuations
118(3)
Combination of all effects and comparison with experiments
121(4)
Discussion
125(1)
Conclusions
126(3)
Technological Aspects
129(24)
Technology descriptions
130(3)
Impact of the gate
133(5)
Amorphous or poly-crystalline silicon as gate material?
133(3)
Impact of the gate doping
136(2)
Impact of the halo implantation
138(7)
Long- and wide-channel transistors
140(3)
Short- and narrow-channel effects
143(2)
Comparison of different CMOS technologies
145(3)
Alternative device concepts
148(2)
Conclusions
150(3)
Impact of Line-Edge Roughness
153(24)
Characterization of line-edge roughness
154(3)
Modeling the impact of line-width roughness
157(6)
Impact of line-width roughness on the threshold voltage
158(2)
Impact of line-width roughness on the off-state current
160(2)
Impact of line-width roughness on yield
162(1)
Experimental investigation of the impact of LWR
163(9)
Experimental setup
163(1)
Sinusoidally-shaped gate edges
164(4)
Extra rough gates
168(3)
Yield
171(1)
Prediction of the impact of LWR and guidelines
172(3)
Conclusions
175(2)
Conclusions, Future Work and Outlook
177(6)
Conclusions
177(2)
Future work
179(2)
Outlook
181(2)
Appendices
183(10)
A List of symbols
183(6)
B List of acronyms
189(2)
C Publications by the author
191(2)
References 193(12)
About the Authors 205

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