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9781402070372

Trade-Offs in Analog Circuit Design

by ; ;
  • ISBN13:

    9781402070372

  • ISBN10:

    1402070373

  • Format: Hardcover
  • Copyright: 2002-09-01
  • Publisher: Kluwer Academic Pub

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Summary

As the frequency of communication systems increases and the dimensions of transistors are reduced, more and more stringent performance requirements are placed on analog circuits. This is a trend that is bound to continue for the foreseeable future and while it does, understanding performance trade-offs will constitute a vital part of the analog design process. It is the insight and intuition obtained from a fundamental understanding of performance conflicts and trade-offs, that ultimately provides the designer with the basic tools necessary for effective and creative analog design. Trade-offs in Analog Circuit Design, which is devoted to the understanding of trade-offs in analog design, is quite unique in that it draws together fundamental material from, and identifies interrelationships within, a number of key analog circuits. The book covers ten subject areas: Design methodology, Technology, General Performance, Filters, Switched Circuits, Oscillators, Data Converters, Transceivers, Neural Processing, and Analog CAD. Within these subject areas it deals with a wide diversity of trade-offs ranging from frequency-dynamic range and power, gain-bandwidth, speed-dynamic range and phase noise, to tradeoffs in design for manufacture and IC layout. The book has by far transcended its original scope and has become both a designer's companion as well as a graduate textbook. An important feature of this book is that it promotes an intuitive approach to understanding analog circuits by explaining fundamental relationships and, in many cases, providing practical illustrative examples to demonstrate the inherent basic interrelationships and trade-offs. Trade-offs in Analog Circuit Design draws together 34 contributions from some of the world's most eminent analog circuits-and-systems designers to provide, for the first time, a comprehensive text devoted to a very important and timely approach to analog circuit design.

Table of Contents

Foreword xxiii
List of Contributors
xxix
Design Methodology
Intuitive Analog Circuit Design
1(6)
Chris Toumazou
Introduction
1(1)
The Analog Dilemma
2(5)
References
6(1)
Design for Manufacture
7(68)
Barrie Gilbert
Mass-Production of Microdevices
7(4)
Present Objectives
9(2)
Unique Challenges of Analog Design
11(3)
Analog is Newtonian
13(1)
Designing with Manufacture in Mind
14(8)
Conflicts and Compromises
15(1)
Coping with Sensitivities: DAPs, TAPs and STMs
16(6)
Robustness, Optimization and Trade-Offs
22(33)
Choice of Architecture
25(2)
Choice of Technology and Topology
27(5)
Remedies for Non-Robust Practices
32(2)
Turning the Tables on a Non-Robust Circuit: A Case Study
34(5)
Holistic optimization of the LNA
39(5)
A further example of biasing synergy
44(6)
Robustness in Voltage References
50(4)
The Cost of Robustness
54(1)
Toward Design Mastery
55(18)
First, the Finale
56(1)
Consider All Deliverables
57(1)
Design Compression
58(3)
Fundamentals before Finesse
61(1)
Re-Utilization of Proven Cells
62(1)
Try to Break Your Circuits
63(1)
Use Corner Modeling Judiciously
64(4)
Use Large-Signal Time-Domain Methods
68(1)
Use Back-Annotation of Parasitics
68(1)
Make Your Intentions Clear
69(1)
Dubious Value of Check Lists
70(2)
Use the ``Ten Things That Will Fail'' Test
72(1)
Conclusion
73(2)
General Performance
Trade-Offs in CMOS VLSI Circuits
75(40)
Andrey V. Mezhiba
Eby G. Friedman
Introduction
75(3)
Design Criteria
78(8)
Area
78(1)
Speed
79(1)
Power
79(1)
Design Productivity
80(1)
Testability
81(1)
Reliability
81(1)
Noise Tolerance
82(1)
Packaging
83(1)
General Considerations
83(1)
Power dissipation in CMOS VLSI circuits
84(1)
Technology scaling
85(1)
VLSI design methodologies
86(1)
Structural Level
86(3)
Parallel Architecture
87(1)
Pipelining
88(1)
Circuit Level
89(10)
Static versus Dynamic
90(1)
Transistor Sizing
91(4)
Tapered Buffers
95(4)
Physical Level
99(3)
Process Level
102(2)
Scaling
103(1)
Threshold Voltage
103(1)
Power Supply
103(1)
Improved Interconnect and Dielectric Materials
104(1)
Future Trends
104(11)
Glossary
107(1)
References
108(7)
Floating-gate Circuits and Systems
115(24)
Tor Sverre Lande
Introduction
115(1)
Device Physics
115(2)
Thin Dioxide
116(1)
Capacitive Connections
116(1)
Special Process Requirements
117(1)
Programming
117(2)
UV-conductance
118(1)
Fowler--Nordheim Tunneling
118(1)
Hot Carrier Injection
119(1)
Circuit Elements
119(9)
Programming Circuits
120(1)
Inter-poly tunneling
120(1)
Example: Floating-gate on-chip knobs
121(1)
Inter-poly UV-programming
121(1)
MOS-transistor UV-conductance
122(1)
Example: MOS transistor threshold tuning
123(1)
Combined programming techniques
124(2)
Example: Single transistor synapse
126(1)
High-voltage drivers
127(1)
FGMOS Circuits and Systems
128(6)
Autozero Floating-Gate Amplifier
128(2)
Low-power/Low-voltage Rail-to-Rail Circuits Using FGUVMOS
130(1)
Digital FGUVMOS circuits
130(1)
Low-voltage rail-to-rail FGUVMOS amplifier
130(2)
Adaptive Retina
132(2)
Other Circuits
134(1)
Retention
134(1)
Concluding Remarks
134(5)
References
135(4)
Bandgap Reference Design
139(30)
Arie van Staveren
Michiel H. L. Kouwenhoven
Wouter A. Serdijn
Chris J. M. Verhoeven
Introduction
139(1)
The Basic Function
140(1)
Temperature Behavior of VBE
140(1)
General Temperature Compensation
141(1)
A Linear Combination of Base-Emitter Voltages
142(4)
First-Order Compensation
143(1)
Second-Order Compensation
144(2)
The Key Parameters
146(1)
Temperature-Dependent Resistors
147(1)
Noise
148(7)
Noise of the Idealized Bandgap Reference
150(1)
Noise of a First-Order Compensated Reference
151(1)
Noise of a Second-Order Compensated Reference
152(1)
Power-Supply Rejection
153(2)
Simplified Structures
155(2)
First-Order Compensated Reference
155(1)
Second-Order Compensated Reference
156(1)
Design Example
157(6)
First-Order Compensated Bandgap Reference
157(2)
Second-Order Compensated Bandgap Reference
159(4)
Conclusions
163(6)
References
164(5)
Generalized Feedback Circuit Analysis
169(38)
Scott K. Burgess
John Choma, Jr.
Introduction
169(2)
Fundamental Properties of Feedback Loops
171(11)
Open Loop System Architecture and Parameters
171(2)
Closed Loop System Parameters
173(3)
Phase Margin
176(3)
Settling Time
179(3)
Circuit Partitioning
182(25)
Generalized Circuit Transfer Function
183(6)
Generalized Driving Point I/O Impedances
189(2)
Special Controlling/Controlled Port Cases
191(1)
Controlling feedback variable is the circuit output variable
192(1)
Global feedback
193(2)
Controlling feedback variable is the branch variable of the controlled port
195(9)
References
204(3)
Analog Amplifiers Architectures: Gain Bandwidth Trade-Offs
207(20)
Alison J. Burdett
Chris Toumazou
Introduction
207(1)
Early Concepts in Amplifier Theory
208(3)
The Ideal Amplifier
208(1)
Reciprocity and Adjoint Networks
209(1)
The Ideal Amplifier Set
210(1)
Practical Amplifier Implementations
211(6)
Voltage Op-Amps
211(2)
Breaking the Gain--Bandwidth Conflict
213(1)
Current-feedback op-amps
213(1)
Follower-based amplifiers
214(1)
Current-conveyor amplifiers
214(1)
Producing a Controlled Output Current
215(2)
Closed-Loop Amplifier Performance
217(5)
Ideal Amplifiers
217(1)
Real Amplifiers
218(4)
Source and Load Isolation
222(2)
Conclusions
224(3)
References
225(2)
Noise, Gain and Bandwidth in Analog Design
227(30)
Robert G. Meyer
Gain--Bandwidth Concepts
227(7)
Gain--Bandwidth Shrinkage
230(2)
Gain--Bandwidth Trade-Offs Using Inductors
232(2)
Device Noise Representation
234(6)
Effect of Inductors on Noise Performance
238(2)
Trade-Offs in Noise and Gain--Bandwidth
240(17)
Methods of Trading Gain for Bandwidth and the Associated Noise Performance Implications [8]
240(3)
The Use of Single-Stage Feedback for the Noise-Gain-Bandwidth Trade-Off
243(5)
Use of Multi-Stage Feedback to Trade-Off Gain, Bandwidth and Noise Performance
248(7)
References
255(2)
Frequency Compensation
257(26)
Arie van Staveren
Michiel H. L. Kouwenhoven
Wouter A. Serdijn
Chris J. M. Verhoeven
Introduction
257(1)
Design Objective
258(2)
The Asymptotic-Gain Model
260(1)
The Maximum Attainable Bandwidth
260(5)
The LP Product
261(2)
The Group of Dominant Poles
263(2)
Pole Placement
265(12)
Resistive Broadbanding
268(2)
Pole--Zero Cancelation
270(2)
Pole Splitting
272(3)
Phantom Zeros
275(2)
Order of Preference
277(1)
Adding Second-Order Effects
277(1)
Example Design
278(3)
Conclusion
281(2)
References
281(2)
Frequency-Dynamic Range-Power
283(32)
Eric A. Vittoz
Yannis P. Tsividis
Introduction
283(1)
Fundamental Limits of Trade-Off
284(15)
Absolute Lower Boundary
284(2)
Filters
286(2)
Oscillators
288(4)
Voltage-to-Current and Current-to-Voltage Conversion
292(3)
Current Amplifiers
295(2)
Voltage Amplifiers
297(2)
Process-Dependent Limitations
299(4)
Parasitic Capacitors
299(1)
Additional Sources of Noise
300(1)
Mismatch of Components
301(1)
Charge Injection
301(1)
Non-Optimum Supply Voltage
302(1)
Companding and Dynamic Biasing
303(7)
Syllabic Companding
303(3)
Dynamic Biasing
306(2)
Performance in the Presence of blockers
308(1)
Instantaneous Companding
309(1)
Conclusion
310(5)
References
311(4)
Filters
Trade-Offs in Sensitivity, Component Spread and Component Tolerance in Active Filter Design
315(26)
George Moschytz
Introduction
315(1)
Basics of Sensitivity Theory
316(3)
The Component Sensitivity of Active Filters
319(6)
Filter Selectivity, Pole Q and Sensitivity
325(3)
Maximizing the Selectivity of RC Networks
328(4)
Some Design Examples
332(5)
Sensitivity and Noise
337(2)
Summary and Conclusions
339(2)
References
339(2)
Continuous-Time Filters
341(14)
Robert Fox
Introduction
341(1)
Filter-Design Trade-Offs: Selectivity, Filter Order, Pole Q and Transient Response
341(1)
Circuit Trade-Offs
342(2)
Linearity vs Tuneability
342(1)
Passive Components
342(1)
Tuneable Resistance Using MOSFETs: The MOSFET-C Approach
343(1)
The Transconductance-C (Gm-C) Approach
344(3)
Triode-Region Transconductors
345(1)
Saturation-Region Transconductors
346(1)
MOSFETs Used for Degeneration
346(1)
BJT-Based Transconductors
347(1)
Offset Differential Pairs
347(1)
Dynamic Range
347(2)
Differential Operation
349(1)
Log-Domain Filtering
349(1)
Transconductor Frequency-Response Trade-Offs
350(1)
Tuning Trade-Offs
351(2)
No tuning
352(1)
Off-chip tuning
352(1)
One-time post-fabrication tuning
352(1)
Automatic tuning
352(1)
Simulation Issues
353(2)
References
353(2)
Insights in Log-Domain Filtering
355(52)
Emmanuel M. Drakakis
Alison J. Burdett
General
355(5)
Synthesis and Design of Log-Domain Filters
360(14)
Impact of BJT Non-Idealities upon Log-Domain Transfer Functions: The Lowpass Biquad Example
374(6)
Floating Capacitor-Based Realization of Finite Transmission Zeros in Log-Domain: The Impact upon Linearity
380(3)
Effect of Modulation Index upon Internal Log-Domain Current Bandwidth
383(7)
Distortion Properties of Log-Domain Circuits: The Lossy Integrator Case
390(3)
Noise Properties of Log-Domain Circuits: The Lossy Integrator Case
393(8)
Summary
401(6)
References
401(6)
Switched Circuits
Trade-offs in the Design of CMOS Comparators
407(36)
A. Rodriguez-Vazquez
M. Delgado-Restituto
R. Dominguez-Castro
F. Medeiro
J.M. de la Rosa
Introduction
407(1)
Overview of Basic CMOS Voltage Comparator Architectures
408(15)
Single-Step Voltage Comparators
409(3)
Multistep Comparators
412(5)
Regenerative Positive-Feedback Comparators
417(4)
Pre-Amplified Regenerative Comparators
421(2)
Architectural Speed vs Resolution Trade-Offs
423(6)
Single-Step Comparators
423(2)
Multistep Comparators
425(1)
Regenerative Comparators
426(3)
On the impact of the offset
429(3)
Offset-Compensated Comparators
432(6)
Offset-Compensation Through Dynamic Biasing
433(2)
Offset Compensation in Multistep Comparators
435(1)
Residual Offset and Gain Degradation in Self-Biased Comparators
436(1)
Transient Behavior and Dynamic Resolution in Self-Biased Comparators
437(1)
Appendix. Simplified MOST Model
438(5)
References
439(4)
Switched-Capacitor Circuits
443(18)
Andrea Baschirotto
Introduction
443(2)
Trade-Off due to Scaled CMOS Technology
445(6)
Reduction of the MOS Output Impedance (ro)
446(1)
Increase of the Flicker Noise
447(1)
Increase of the MOS Leakage Current
447(1)
Reduction of the Supply Voltage
448(3)
Trade-Off in High-Frequency SC Circuits
451(5)
Trade-Off Between an IIR and a FIR Frequency Response
452(1)
Trade-Off in SC Parallel Solutions
453(1)
Trade-Off in the Frequency Choice
454(2)
Conclusions
456(5)
Acknowledgments
456(1)
References
457(4)
Compatibility of SC Technique with Digital VLSI Technology
461(30)
Kritsapon Leelavattananon
Chris Toumazou
Introduction
461(1)
Monolithic MOS Capacitors Available in Digital VLSI Processes
461(5)
Polysilicon-over-Polysilicon (or Double-Poly) Structure
462(1)
Polysilicon-over-Diffusion Structure
462(1)
Metal-over-Metal Structure
463(1)
Metal-over-Polysilicon Structure
464(1)
MOSFET Gate Structure
464(2)
Operational Amplifiers in Standard VLSI Processes
466(8)
Operational Amplifier Topologies
466(1)
Single-stage (telescopic) amplifier
466(1)
Folded cascode amplifier
466(1)
Gain-boosting amplifier
467(1)
Two-stage amplifier
468(1)
Frequency Compensation
469(1)
Miller compensation
469(1)
Miller compensation incorporating source follower
470(1)
Cascode Miller Compensation
471(1)
Common-Mode Feedback
472(2)
Charge-Domain Processing
474(3)
Linearity Enhanced Composite Capacitor Branches
477(8)
Series Compensation Capacitor Branch
480(2)
Parallel Compensation Capacitor Branch
482(1)
Balanced Compensation Capacitor Branch
483(2)
Practical Considerations
485(2)
Bias Voltage Mismatch
485(1)
Capacitor Mismatch
485(1)
Parasitic Capacitances
486(1)
Summary
487(4)
References
488(3)
Switched-Capacitors or Switched-Currents -- Which Will Succeed?
491(26)
John Hughes
Apisak Worapishet
Introduction
491(1)
Test Vehicles and Performance Criteria
492(2)
Clock Frequency
494(5)
Switched-Capacitor Settling
495(2)
Switched-Currents Class A Settling
497(1)
Switched-Currents Class AB Settling
498(1)
Power Consumption
499(1)
Switched-Capacitors and Switched-Currents Class A Power Consumption
499(1)
Switched-Currents Class AB Power Consumption
499(1)
Signal-to-Noise Ratio
499(10)
Switched-Capacitors Noise
500(3)
Switched-Currents Class A Noise
503(3)
Switched-Current Class AB Noise
506(1)
Comparison of Signal-to-Noise Ratios
507(2)
Figure-of-Merit
509(1)
Switched-Capacitors
509(1)
Switched-Currents Class A
510(1)
Switched-Currents Class AB
510(1)
Comparison of Figures-of-Merit
510(4)
Conclusions
514(3)
References
514(3)
Oscillators
Design of Integrated LC VCOs
517(34)
Donhee Ham
Introduction
517(1)
Graphical Nonlinear Programming
518(1)
LC VCO Design Constraints and an Objective Function
519(7)
Design Constraints
522(1)
Phase Noise as an Objective Function
522(1)
Phase Noise Approximation
523(2)
Independent Design Variables
525(1)
LC VCO Optimization via GNP
526(11)
Example of Design Constraints
527(1)
GNP with a Fixed Inductor
527(3)
GNP with a Fixed Inductance Value
530(3)
Inductance and Current Selection
533(2)
Summary of the Optimization Process
535(1)
Remarks on Final Adjustment and Robust Design
536(1)
Discussion on LC VCO Optimization
537(3)
Simulation
540(1)
Experimental Results
541(4)
Conclusion
545(6)
Acknowledgments
546(1)
References
546(5)
Trade-Offs in Oscillator Phase Noise
551(40)
Ali Hajimiri
Motivation
551(1)
Measures of Frequency Instability
551(6)
Phase Noise
554(2)
Timing Jitter
556(1)
Phase Noise Modeling
557(8)
Up-Conversion of 1/f Noise
562(1)
Time-Varying Noise Sources
563(2)
Phase Noise Trade-Offs in LC Oscillators
565(9)
Tank Voltage Amplitude
565(5)
Noise Sources
570(1)
Stationary noise approximation
570(2)
Cyclostationary noise sources
572(1)
Design Implications
573(1)
Phase Noise Trade-Offs for Ring Oscillators
574(17)
The Impulse Sensitivity Function for Ring Oscillators
574(5)
Expressions for Phase Noise in Ring Oscillators
579(3)
Substrate and Supply Noise
582(2)
Design Trade-Offs in Ring Oscillators
584(1)
References
585(6)
Data Converters
Systematic Design of High-Performance Data Converters
591(22)
Georges Gielen
Jan Vandenbussche
Geert van der Plas
Walter Daems
Anne Van den Bosch
Michiel Steyaert
Willy Sansen
Introduction
591(1)
Systematic Design Flow for D/A Converters
592(2)
Current-Steering D/A Converter Architecture
594(3)
Generic Behavioral Modeling for the Top-Down Phase
597(2)
Sizing Synthesis of the D/A Converter
599(4)
Architectural-Level Synthesis
600(1)
Static performance
600(1)
Dynamic performance
601(1)
Circuit-Level Synthesis
602(1)
Static performance
602(1)
Dynamic performance
603(1)
Full Decoder Synthesis
603(1)
Clock Driver Synthesis
603(1)
Layout Synthesis of the D/A Converter
603(3)
Floorplanning
604(1)
Circuit and Module Layout Generation
604(1)
Current-source array layout generation
604(1)
Swatch array layout generation
605(1)
Full decoder standard cell place and route
605(1)
Converter Layout Assembly
606(1)
Extracted Behavioral Model for Bottom-Up Verification
606(1)
Experimental Results
607(3)
Conclusions
610(3)
Acknowledgments
610(1)
References
610(3)
Analog Power Modeling for Data Converters and Filters
613(18)
Georges Gielen
Erik Lauwers
Introduction
613(1)
Approaches for Analog Power Estimators
614(2)
A Power Estimation Model for High-Speed Nyquist-Rate ADCs
616(4)
The Power Estimator Derivation
616(3)
Results of the Power Estimator
619(1)
A Power Estimation Model for Analog Continuous-Time Filters
620(7)
The ACTIF Approach
620(1)
Description of the Filter Synthesis Part
621(3)
OTA Behavioral Modeling and Optimization for Minimal Power Consumption
624(1)
Modeling of the transconductances
624(1)
The distortion model
625(1)
Optimization
626(1)
Experimental Results
627(1)
Conclusions
627(4)
Acknowledgment
628(1)
References
628(3)
Speed vs. dynamic range Trade-Off in Oversampling Data Converters
631(34)
Richard Schreier
Jesper Steensgaard
Gabor C. Temes
Introduction
631(1)
Oversampling Data Converters
632(12)
Quantization Error
632(1)
Feedback Quantizers
633(3)
Oversampling D/A Converters
636(3)
Oversampling A/D Converters
639(1)
Multibit Quantization
640(4)
Mismatch Shaping
644(9)
Element Rotation
644(1)
Generalized Mismatch-Shaping
645(4)
Other Mismatch-Shaping Architectures
649(1)
Performance Comparison
650(3)
Reconstructing a Sampled Signal
653(12)
The Interpolation Process
654(1)
An interpolation system example
654(2)
Fundamental Architectures for Practical Implementations
656(1)
Single-bit delta-sigma modulation
657(1)
Multibit delta-sigma modulation
657(1)
High-resolution oversampled D/A converters
658(1)
High-Resolution Mismatch-Shaping D/A Converters
659(1)
A fresh look on mismatch shaping
659(1)
Practical implementations
660(2)
References
662(3)
Transceivers
Power-Conscious Design of Wireless Circuits and Systems
665(32)
Asad A. Abidi
Introduction
665(2)
Lowering Power across the Hierarchy
667(1)
Power Conscious RF and Baseband Circuits
668(29)
Dynamic Range and Power Consumption
668(2)
Lowering Power in Tuned Circuits
670(1)
Importance of Passives Quality in Resonant Circuits
671(2)
Low Noise Amplifiers
673(5)
Oscillators
678(3)
Mixers
681(4)
Frequency Dividers
685(1)
Baseband Circuits
686(3)
On-Chip Inductors
689(2)
Examples of Low Power Radio Implementations
691(1)
Conclusions: Circuits
692(1)
References
692(5)
Photoreceiver Design
697(26)
Mark Forbes
Introduction
697(1)
Review of Receiver Structure
698(2)
Front-End Small-Signal Performance
700(7)
Small-Signal Analysis
700(2)
Speed/Sensitivity Trade-Off
702(4)
Calculations, for example, parameters
706(1)
Noise Limits
707(2)
Post-Amplifier Performance
709(3)
Front-End and Post-Amplifier Combined Trade-Off
712(2)
Mismatch
714(4)
Conclusions
718(5)
Acknowledgments
718(1)
References
719(4)
Analog Front-End Design Considerations for DSL
723(24)
Nianxiong Nick Tan
Introduction
723(2)
System Considerations
725(3)
Digital vs Analog Process
725(1)
Active vs Passive Filters
726(2)
Data Converter Requirements for DSL
728(12)
Optimum Data Converters for ADSL
732(1)
Optimum ADCs for ADSL
732(2)
Optimum ADC for ADSL-CO
734(1)
Optimum ADC for ADSL-CP
735(1)
Optimum DACs
735(2)
Optimum DAC for ADSL-CO
737(1)
Optimum DAC for ADSL-CP
737(1)
Function of Filtering
738(2)
Circuit Considerations
740(4)
Oversampling vs Nyquist Data Converters
740(3)
SI vs SC
743(1)
Sampled-Data vs Continuous-Time Filters
743(1)
Gm-C vs RC filters
744(1)
Conclusions
744(3)
Acknowledgments
745(1)
References
745(2)
Low Noise Design
747(40)
Michiel H. L. Kouwenhoven
Arie van Staveren
Wouter A. Serdijn
Chris J. M. Verhoeven
Introduction
747(1)
Noise Analysis Tools
747(4)
Equivalent Noise Source
748(1)
Transform-I: Voltage Source Shift
749(1)
Transform-II: Current Source Shift
749(1)
Transform-III: Norton--Thevenin Transform
749(1)
Transform-IV: Shift through Twoports
750(1)
Low-Noise Amplifier Design
751(11)
Design of the Feedback Network
752(1)
Noise production by the feedback network
753(1)
Magnification of nullor noise
754(1)
Distortion increment and bandwidth reduction
755(1)
Design of the Active Part for Low Noise
756(1)
Noise Optimizations
757(1)
Noise matching to the source
757(2)
Optimization of the bias current
759(1)
Connecting stages in series/parallel
760(1)
Summary of optimizations
761(1)
Low Noise Harmonic Resonator Oscillator Design
762(10)
General Structure of a Resonator Oscillator
762(1)
Noise Contribution of the Resonator
763(1)
Design of the Undamping Circuit for Low Noise
764(1)
Principle implementation of the undamping circuit
765(1)
Amplitude control
765(1)
Noise performance
766(1)
Driving the oscillator load
766(1)
Noise Matching of the Resonator and Undamping Circuit: Tapping
767(2)
Power Matching
769(1)
Coupled Resonator Oscillators
770(2)
Low-Noise Relaxation Oscillator Design
772(15)
Phase Noise in Relaxation Oscillators
773(1)
Simple phase noise model
773(1)
Influence of the memory on the oscillator phase noise
774(2)
Influence of comparators on the oscillator phase noise
776(1)
Improvement of the Noise Behavior by Alternative Topologies
777(1)
Relaxation oscillators with memory bypass
778(2)
Coupled relaxation oscillators
780(4)
References
784(3)
Trade-Offs in CMOS Mixer Design
787(34)
Ganesh Kathiresan
Chris Toumazou
Introduction
787(2)
The RF Receiver Re-Visited
788(1)
Some Mixer Basics
789(3)
Mixers vs Multipliers
789(2)
Mixers: Nonlinear or Linear-Time-Variant?
791(1)
Mixer Figures of Merit
792(8)
Conversion Gain and Bandwidth
793(1)
1 dB Compression Point
794(2)
Third-Order Intercept Point
796(1)
Noise Figure
797(2)
Port-to-Port Isolation
799(1)
Common Mode Rejection, Power Supply, etc
799(1)
Mixer Architectures and Trade-Offs
800(17)
Single Balanced Differential Pair Mixer
800(3)
Double-Balanced Mixer and Its Conversion Gain
803(2)
Supply Voltage
805(1)
Active loads
805(1)
Inductive current source
805(1)
Two stack source coupled mixer
806(1)
Bulk driven topologies
807(2)
Linearity
809(1)
Source degeneration
809(2)
Switched MOSFET degeneration
811(1)
LO Feedthrough
812(1)
Mixer Noise
813(1)
Noise due to the load
814(1)
Noise due to the input transconductor
814(1)
Noise due to the switches
815(2)
Conclusion
817(4)
References
817(4)
A High-performance Dynamic-logic Phase-Frequency Detector
821(22)
Shenggao Li
Mohammed Ismail
Introduction
821(1)
Phase Detectors Review
822(5)
Multiplier
822(1)
Exclusive-OR Gate
823(2)
JK-Flipflop
825(1)
Tri-State Phase Detector
825(2)
Design Issues in Phase-Frequency Detectors
827(4)
Dead-Zone
827(2)
Blind-Zone
829(2)
Dynamic Logic Phase-Frequency Detectors
831(4)
A Novel Dynamic-Logic Phase-Frequency Detector
835(7)
Circuit Operation
836(1)
Performance Evaluation
837(5)
Conclusion
842(1)
References
842(1)
Trade-Offs in Power Amplifiers
843(40)
Chung Kei Thomas Chan
Steve Hung-Lung Tu
Chris Toumazou
Introduction
843(2)
Classification of Power Amplifiers
845(8)
Current-Source Power Amplifiers
845(3)
Switch-Mode Power Amplifiers
848(1)
Class D power amplifier
848(1)
Class E power amplifier
849(1)
Class F power amplifier
850(2)
Bandwidth Efficiency, Power Efficiency and Linearity
852(1)
Effect of Loaded Q-Factor on Class E Power Amplifiers
853(8)
Circuit Analysis
853(4)
Power Efficiency
857(1)
Circuit Simulation and Discussion
858(3)
Class E Power Amplifiers with Nonlinear Shunt Capacitance
861(17)
Numerical Computation of Optimum Component Values
863(1)
Basic equations
863(2)
Optimum operation (Alinikula's method [16])
865(4)
Fourier analysis
869(1)
Normalized power capability
869(1)
Generalized Numerical Method
870(2)
Design example
872(1)
Small linear shunt capacitor
872(6)
Conclusion
878(5)
References
880(3)
Neural Processing
Trade-Offs in Standard and Universal CNN Cells
883(40)
Martin Hanggi
Radu Dogaru
Leon O. Chua
Introduction
883(1)
The Standard CNN
884(3)
Circuit Implementation of CNNs
886(1)
Standard CNN Cells: Robustness vs Processing Speed
887(15)
Reliability of a Standard CNN
887(1)
Introduction
887(1)
Absolute and relative robustness
888(1)
The Robustness of a CNN template set
888(2)
Template scaling
890(1)
Template design
890(2)
The Settling Time of a Standard CNN
892(1)
Introduction
892(1)
The exact approach for uncoupled CNNS
893(1)
Analysis of Propagation-Type Templates
893(1)
Introduction
893(1)
Examples of propagation-type templates
894(3)
Robust CNN Algorithms for High-Connectivity Tasks
897(1)
Template classes
898(2)
One-step vs algorithmic processing
900(1)
Concluding Remarks
901(1)
Universal CNN Cells and their Trade-Offs
902(21)
Preliminaries
902(2)
Pyramidal CNN cells
904(1)
Architecture
904(1)
Trade-offs
905(1)
Canonical Piecewise-linear CNN cells
906(1)
Characterization and architecture
906(1)
Trade-offs
907(1)
Example
908(1)
The Multi-Nested Universal CNN Cell
909(1)
Architecture and characterization
909(1)
Trade-offs
910(4)
An RTD-Based Multi-Nested Universal CNN Cell Circuit
914(3)
Concluding Remarks
917(1)
References
918(5)
Analog CAD
Top-Down Design Methodology For Analog Circuits Using Matlab and Simulink
923(30)
Naveen Chandra
Gordon W. Roberts
Introduction
923(2)
Design Methodology Motivation
925(2)
Optimization Procedure
926(1)
Switched Capacitor Delta-Sigma Design Procedure
927(2)
Switched Sampled Capacitor (kT/C) Noise
928(1)
OTA Parameters
929(1)
Modeling of ΔΣ Modulators in Simulink
929(9)
Sampled Capacitor (kT/C) Noise
930(1)
OTA Noise
931(1)
Switched Capacitor Integrator Non-Idealities
932(6)
Optimization Setup
938(7)
Implementation in Matlab
941(2)
Initial Conditions
943(2)
Additional Factors
945(1)
Summary of Simulation Results
945(1)
A Fully Coded ΔΣ Modulator Design Example
946(4)
Conclusion
950(3)
References
951(2)
Techniques and Applications of Symbolic Analysis for Analog Integrated Circuits
953(32)
Georges Gielen
Introduction
953(1)
What is Symbolic Analysis?
953(5)
Definition of Symbolic Analysis
953(3)
Basic Methodology of Symbolic Analysis
956(2)
Applications of Symbolic Analysis
958(7)
Insight into Circuit Behavior
958(2)
Analytic Model Generation for Automated Analog Circuit Sizing
960(1)
Interactive Circuit Exploration
961(1)
Repetitive Formula Evaluation
961(1)
Analog Fault Diagnosis
962(1)
Behavioral Model Generation
963(1)
Formal Verification
964(1)
Summary of Applications
965(1)
Present Capabilities and Limitations of Symbolic Analysis
965(11)
Symbolic Approximation
966(2)
Improving Computational Efficiency
968(1)
Simplification During Generation
969(2)
Simplification Before Generation
971(1)
Hierarchical Decomposition
971(3)
Symbolic Pole-Zero Analysis
974(1)
Symbolic Distortion Analysis
974(2)
Open Research Topics
976(1)
Comparison of Symbolic Simulators
976(1)
Conclusions
977(8)
Acknowledgments
979(1)
References
979(6)
Topics in IC Layout for Manufacture
985(48)
Barrie Gilbert
Layout: The Crucial Next Step
985(11)
An Architectural Analogy
988(1)
IC Layout: A Matter of ``Drafting''?
989(3)
A Shared Undertaking
992(1)
What Inputs should the Layouteer Expect?
993(3)
Interconnects
996(10)
Metal Limitations
998(2)
Other Metalization Trade-Offs
1000(6)
Substrates and the Myth of ``Ground''
1006(4)
Device-Level Substrate Nodes
1009(1)
Starting an Analog Layout
1010(2)
Device Matching
1012(12)
The ``Biggest-of-All'' Layout Trade-Off
1015(1)
Matching Rules for Specific Components
1016(2)
Capacitor Matching
1018(2)
Circuit/Layout Synergy
1020(4)
Layout of Silicon-on-Insulator Processes
1024(5)
Consequences of High Thermal Resistance
1028(1)
Reflections on Superintegrated Layout
1029(4)
Index 1033

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