did-you-know? rent-now

Amazon no longer offers textbook rentals. We do!

did-you-know? rent-now

Amazon no longer offers textbook rentals. We do!

We're the #1 textbook rental company. Let us show you why.

9783540284741

Cryptographic Hardware And Embedded Systems - Ches 2005: 7th International Workshop, Edinburgh, Uk, August 29 - September 1, 2005, Proceedings

by ;
  • ISBN13:

    9783540284741

  • ISBN10:

    3540284745

  • Format: Paperback
  • Copyright: 2005-10-16
  • Publisher: Springer Verlag
  • Purchase Benefits
List Price: $129.00

Summary

This book constitutes the refereed proceedings of the 7th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2005, held in Edinburgh, UK in August/September 2005. The 32 revised full papers presented were carefully reviewed and selected from 108 submissions. The papers are organized in topical sections on side channels, arithmetic for cryptanalysis, low resources, special purpose hardware, hardware attacks and countermeasures, arithmetic for cryptography, trusted computing, and efficient hardware.

Table of Contents

Side Channels I
Resistance of Randomized Projective Coordinates Against Power Analysis
William Dupuy, Sébastien Kunz-Jacques
1(14)
Templates as Master Keys
Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm
15(15)
A Stochastic Model for Differential Side Channel Cryptanalysis
Werner Schindler, Kerstin Lemke, Christof Paar
30(17)
Arithmetic for Cryptanalysis
A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis
Jean Sébastien Coron, David Lefranc, Guillaume Poupard
47(14)
Further Hidden Markov Model Cryptanalysis
P.J. Green, R. Noad, N.P. Smart
61(14)
Low Resources
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
Johann Großschädl, Roberto M. Avanzi, Erkay Savas, Stefan Tillich
75(16)
Short Memory Scalar Multiplication on Koblitz Curves
Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume
91(15)
Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 μP
Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede
106(13)
Special Purpose Hardware
SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers
Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Cohn Stahlke
119(12)
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer
131(16)
Design of Testable Random Bit Generators
Marco Bucci, Raimondo Luzzi
147(10)
Hardware Attacks and Countermeasures I
Successfully Attacking Masked AES Hardware Implementations
Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald
157(15)
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
Thomas Popp, Stefan Mangard
172(15)
Masking at Gate Level in the Presence of Glitches
Wieland Fischer, Berndt M. Gammel
187(14)
Arithmetic for Cryptography
Bipartite Modular Multiplication
Marcelo E. Kaihara, Naofumi Takagi
201(10)
Fast Truncated Multiplication for Cryptographic Applications
Laszlo Hars
211(15)
Using an RSA Accelerator for Modular Inversion
Martin Seysen
226(11)
Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
B. Sunar, D. Cyganski
237(13)
Side Channel II (EM)
EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA
Catherine H. Gebotys, Simon Ho, C.C. Tiu
250(15)
Security Limits for Compromising Emanations
Markus G. Kuhn
265(15)
Security Evaluation Against Electromagnetic Analysis at Design Time
Huiyun Li, A. Theodore Markettos, Simon Moore
280(13)
Side Channel III
On Second-Order Differential Power Analysis
Marc Joye, Pascal Paillier, Berry Schoenmakers
293(16)
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater
309(15)
Trusted Computing
Secure Data Management in Trusted Computing
Ulrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble
324(15)
Hardware Attacks and Countermeasures II
Data Remanence in Flash Memory Devices
Sergei Skorobogatov
339(15)
Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment
Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede
354(12)
Hardware Attacks and Countermeasures III
DPA Leakage Models for CMOS Logic Circuits
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
366(17)
The "Backend Duplication" Method
Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
383(15)
Efficient Hardware I
Hardware Acceleration of the Tate Pairing in Characteristic Three
P. Grabher, D. Page
398(14)
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
T. Kerins, W.P. Marnane, E.M. Popovici, P.S.L.M. Barreto
412(15)
Efficient Hardware II
AES on FPGA from the Fastest to the Smallest
Tim Good, Mohammed Benaissa
427(14)
A Very Compact S-Box for AES
D. Canright
441(16)
Author Index 457

Supplemental Materials

What is included with this book?

The New copy of this book will include any supplemental materials advertised. Please check the title of the book to determine if it should include any access cards, study guides, lab manuals, CDs, etc.

The Used, Rental and eBook copies of this book are not guaranteed to include any supplemental materials. Typically, only the book itself is included. This is true even if the title states it includes any access cards, study guides, lab manuals, CDs, etc.

Rewards Program